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advisory august 5, 1999 tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 5 of the device register architecture (ra) map ra-1. reset bit the software reset bit (bit 0) of register 0x00 is not functional. ra-2. transmit path ais insert bit the txpaisins bit (bit 5) of register 0x01 produces both ais-p and ais-l. ra-3. sts-1 loss of pointer mask bit the sts1lopmsk bit (bit 2) of register 0x04 masks both sts1lop and sts1lof. ra-4. sts-1 loss of frame mask bit the sts1lofmsk bit (bit 1) of register 0x04 is not functional. ra-5. vtlabcom and vtrfirdicom interrupt bits occasionally, it might require multiple reads to clear the composite interrupt bits vtlabcom (bit 2 of register 0x05) and vtrfirdicom (bit 4 of register 0x05). error insertion (ei) ei-1. ds1/e1 alarm indication signal the device does not insert ds1/e1 ais towards the sts-1 if there is an loc condition in the incoming ds1/e1 signal. ei-2. loc condition in e1 loopback mode in the absence of an input clock, the device detects an loc condition and generates tu-ais upstream, even if the loopback path is selected (the loopback signal is overwritten by tu-ais).
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved august 5, 1999 ay99-025sont (must accompany ds99-068sont) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) tmpr28051 sts-1/au-3 ( stm-0 ) ma pp er advisor y device advisor y for version 5 of the device au g ust 5, 1999 error insertion ( ei ) ( continued ) ei-3. false s-bip, l-bip, and p-bip error insertion the device transmits s-bip, l-bip, and p-bip errors when confi g ured for automatic insertion of rei, and certain sts-1 error conditions such as los, lof, lop-p, s-bip, l-bip, and p-bip are inserted. vt alarms ( vt ) vt-1. vt path pa y load label mismatch the device reports plm-v when it detects three consecutive consistent new values for the vt label. this is in com- pliance with g.783 section 2.2.2.7 and t1.231 section 8.1.3.5.2.4.2 specifications, but is not compliant with gr-253 section 6.2.1.1.8.c. vt-2. failure in the detection of vt loss of pointer defects the device also apparentl y fails to detect an lop-v defect when it continuousl y receives a vt pointer word of 6c68 ( i.e., a value indicatin g a vt1.5 with an offset of 104 b y tes, versus a maximum valid offset of 103 b y tes ) . in this case, the device inserts the re q uired ds1 ais downstream, but does not subse q uentl y declare an lop-v fail- ure ( nonconformance to gr 253, r6-71 ) . vt-3. ina pp ro p riate termination of vt loss of pointer defect condition after the device has detected an lop-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer. accordin g to gr 253, an lop-v defect must not be terminated unless a valid pointer is received in three consecutive vt superframes ( nonconformance to gr 253, r6-75 ) . vt-4. ina pp ro p riate termination of vt alarm indication si g nal defect condition after the device has detected an ais-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer and without a set ndf ( e. g ., with the n bits set to 0110 ) . accordin g to gr 253, an ais-v defect must not be terminated unless a normal valid pointer is received in three consecutive vt superframes, or a valid pointer with a set ndf is received in one vt superframe ( nonconfor- mance to gr 253, r6-183 ) .
tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 2 of the device advisory, rev. 2 august 5, 1999 re g ister architecture ( ra ) ma p ra-1. reset bit the software reset bit (bit 0) of register 0x00 is not functional. ra-2. transmit path ais insert bit the txpaisins bit (bit 5) of register 0x01 produces both ais-p and ais-l. ra-3. sts-1 loss of pointer mask bit the sts1lopmsk bit (bit 2) of register 0x04 masks both sts1lop and sts1lof. ra-4. sts-1 loss of frame mask bit the sts1lofmsk bit (bit 1) of register 0x04 is not functional. ra-5. vtlabcom and vtrfirdicom interru p t bits occasionally, it might require multiple reads to clear the composite interrupt bits vtlabcom (bit 2 of register 0x05) and vtrfirdicom (bit 4 of register 0x05). error insertion ( ei ) ei-1. ds1/e1 alarm indication si g nal the device does not insert ds1/e1 ais towards the sts-1 if there is an loc condition in the incoming ds1/e1 signal. ei-2. loc condition in e1 loo p back mode in the absence of an input clock, the device detects an loc condition and generates tu-ais upstream, even if the loopback is selected (the loopback signal is overwritten by tu-ais).
tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 2 of the device august 5, 1999 2 lucent technologies inc. error insertion ( ei ) ( continued ) ei-3. false s-bip, l-bip, and p-bip error insertion the device transmits s-bip, l-bip, and p-bip errors when confi g ured for automatic insertion of rei, and certain sts-1 error conditions such as los, lof, lop-p, s-bip, l-bip, and p-bip are inserted. ei-4. forcin g ais condition in order to force ais usin g the vtdrop bits, a value of 0x1d must be pro g rammed for ds1 ais, and a value of 0x1e must be pro g rammed for e1 ais. vt ma pp in g ( vt ) vt-1. vt path pa y load label mismatch the device reports plm-v when it detects three consecutive consistent new values for the vt label. this is in com- pliance with g.783 section 2.2.2.7 and t1.231 section 8.1.3.5.2.4.2 specifications, but is not compliant with gr-253 section 6.2.1.1.8.c. vt-2. failure in the detection of vt loss of pointer defects n the device fails to detect an lop-v defect or insert the re q uired ds1/e1 ais downstream when it receives vt pointer words with the n bits continuousl y set to 1001 ( i.e., with a continuousl y set ndf ) . n the device also apparentl y fails to detect an lop-v defect when it continuousl y receives a vt pointer word of 6c68 ( i.e., a value indicatin g a vt1.5 with an offset of 104 b y tes, versus a maximum valid offset of 103 b y tes ) . in this case, the device inserts the re q uired ds1 ais downstream, but does not subse q uentl y declare an lop-v failure ( nonconformance to gr 253, r6-71 ) . vt-3. ina pp ro p riate termination of vt loss of pointer defect condition after the device has detected an lop-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer. accordin g to gr 253, an lop-v defect must not be terminated unless a valid pointer is received in three consecutive vt superframes ( nonconformance to gr 253, r6-75 ) . vt-4. ina pp ro p riate termination of vt alarm indication si g nal defect condition after the device has detected an ais-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer and without a set ndf ( e. g ., with the n bits set to 0110 ) . accordin g to gr 253, an ais-v defect must not be terminated unless a normal valid pointer is received in three consecutive vt superframes, or a valid pointer with a set ndf is received in one vt superframe ( nonconfor- mance to gr 253, r6-183 ) .
advisory, rev. 2 tmpr28051 sts-1/au-3 (stm-0) mapper august 5, 1999 device advisory for version 2 of the device 3 lucent technologies inc. vt ma pp in g ( vt ) ( continued ) vt-5. c-bit decodin g in the presence of a receive sonet/sdh bit error rate, the device ma y destuff the ds1 from the vt1.5 incorrectl y . this is the result of an error in the vt1.5 c-bit decodin g process. the c-bit decodin g process should be capable of correctin g sin g le errors to the c bits. because of this error, an error in the first or second c bit for position 2 will be incorrectl y decoded if the first c-bit position is callin g for a stuff and the second c-bit position is not. the end result of this error is that both positions will call for a stuff, resultin g in a bit bein g removed from the ds1 data stream. this will force downstream e q uipment to experience a reframe. the minimum time to false decode severit y is as shown in table vt-5 ( in terms of seconds to false decode ) . table vt-5. minimum time ( in seconds ) to false decode severit y of the c bit in the absence of an external bit error rate, the al g orithm decodes these c bits correctl y . test pattern ( tp ) generator/monitor tp-1. test pattern insert the transmitted test pattern comes out on the opposite ed g e with respect to the j itter-attenuated data. tp-2. test pattern dro p the test pattern detector alwa y s inverts the clock comin g into the block before retimin g the data. jitter attenuation ( ja ) ja-1. jitter attenuator the di g ital j itter attenuator buffers are not functional. the djactl bit in re g ister 0x01 should be set to 0 in this device. puttin g the device in the j itter attenuator mode ( djactl = 1 ) causes loss of transmission. ber theoretical actual 10 C3 125 0.25 10 C4 12500 2.5 10 C5 1250000 25 10 C6 1.25e+8 250 10 C7 1.25e+10 2500 10 C8 1.25e+12 2.5e+4 10 C9 1.25e+14 2.5e+5 10 C10 1.25e+16 2.5e+6
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved august 5, 1999 ay99-026sont-2 (replaces ay99-026sont and must accompany ds99-068sont) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 2 of the device august 5, 1999 sts path overhead ( poh ) poh-1. false h4lomf indication forcin g a sonet/sdh line level decrement ( h1, h2 ) from a value of either 348 or 347 results in false h4lomf indications. loss of data ( lod ) lod-1. loss of ds1/e1 data simultaneousl y forcin g vt pointer ad j ustments while forcin g sonet/sdh decrements from values of 348 and 347 results in loss of ds1/e1 data. ay99-026sont-2 re p laces ay99-026sont to incor p orate the followin g u p dates added issues ra-5 and ei-3 to the document.
tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 3 of the device advisory, rev. 2 august 5, 1999 re g ister architecture ( ra ) ma p ra-1. reset bit the software reset bit (bit 0) of register 0x00 is not functional. ra-2. transmit path ais insert bit the txpaisins bit (bit 5) of register 0x01 produces both ais-p and ais-l. ra-3. sts-1 loss of pointer mask bit the sts1lopmsk bit (bit 2) of register 0x04 masks both sts1lop and sts1lof. ra-4. sts-1 loss of frame mask bit the sts1lofmsk bit (bit 1) of register 0x04 is not functional. ra-5. vtlabcom and vtrfirdicom interru p t bits occasionally, it might require multiple reads to clear the composite interrupt bits vtlabcom (bit 2 of register 0x05) and vtrfirdicom (bit 4 of register 0x05). error insertion ( ei ) ei-1. ds1/e1 alarm indication si g nal the device does not insert ds1/e1 ais towards the sts-1 if there is an loc condition in the incoming ds1/e1 signal. ei-2. loc condition in e1 loo p back mode in the absence of an input clock, the device detects an loc condition and generates tu-ais upstream, even if the loopback is selected (the loopback signal is overwritten by tu-ais).
tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 3 of the device august 5, 1999 2 lucent technologies inc. error insertion ( ei ) ( continued ) ei-3. false s-bip, l-bip, and p-bip error insertion the device transmits s-bip, l-bip, and p-bip errors when confi g ured for automatic insertion of rei, and certain sts-1 error conditions such as los, lof, lop-p, s-bip, l-bip, and p-bip are inserted. ei-4. forcin g ais condition in order to force ais usin g the vtdrop bits, a value of 0x1d must be pro g rammed for ds1 ais, and a value of 0x1e must be pro g rammed for e1 ais. vt ma pp in g ( vt ) vt-1. vt path pa y load label mismatch the device reports plm-v when it detects three consecutive consistent new values for the vt label. this is in com- pliance with g.783 section 2.2.2.7 and t1.231 section 8.1.3.5.2.4.2 specifications, but is not compliant with gr-253 section 6.2.1.1.8.c. vt-2. failure in the detection of vt loss of pointer defects n the device fails to detect an lop-v defect or insert the re q uired ds1/e1 ais downstream when it receives vt pointer words with the n bits continuousl y set to 1001 ( i.e., with a continuousl y set ndf ) . n the device also apparentl y fails to detect an lop-v defect when it continuousl y receives a vt pointer word of 6c68 ( i.e., a value indicatin g a vt1.5 with an offset of 104 b y tes, versus a maximum valid offset of 103 b y tes ) . in this case, the device inserts the re q uired ds1 ais downstream, but does not subse q uentl y declare an lop-v failure ( nonconformance to gr 253, r6-71 ) . vt-3. ina pp ro p riate termination of vt loss of pointer defect condition after the device has detected an lop-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer. accordin g to gr 253, an lop-v defect must not be terminated unless a valid pointer is received in three consecutive vt superframes ( nonconformance to gr 253, r6-75 ) . vt-4. ina pp ro p riate termination of vt alarm indication si g nal defect condition after the device has detected an ais-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer and without a set ndf ( e. g ., with the n bits set to 0110 ) . accordin g to gr 253, an ais-v defect must not be terminated unless a normal valid pointer is received in three consecutive vt superframes, or a valid pointer with a set ndf is received in one vt superframe ( nonconfor- mance to gr 253, r6-183 ) .
advisory, rev. 2 tmpr28051 sts-1/au-3 (stm-0) mapper august 5, 1999 device advisory for version 3 of the device 3 lucent technologies inc. vt ma pp in g ( vt ) ( continued ) vt-5. c-bit decodin g in the presence of a receive sonet/sdh bit error rate, the device ma y destuff the ds1 from the vt1.5 incorrectl y . this is the result of an error in the vt1.5 c-bit decodin g process. the c-bit decodin g process should be capable of correctin g sin g le errors to the c bits. because of this error, an error in the first or second c bit for position 2 will be incorrectl y decoded if the first c-bit position is callin g for a stuff and the second c-bit position is not. the end result of this error is that both positions will call for a stuff, resultin g in a bit bein g removed from the ds1 data stream. this will force downstream e q uipment to experience a reframe. the minimum time to false decode severit y is as shown in table vt-5 ( in terms of seconds to false decode ) . table vt-5. minimum time ( in seconds ) to false decode severit y of the c bit in the absence of an external bit error rate, the al g orithm decodes these c bits correctl y . test pattern ( tp ) generator/monitor tp-1. test pattern insert the transmitted test pattern comes out on the opposite ed g e with respect to the j itter-attenuated data. tp-2. test pattern dro p the test pattern detector alwa y s inverts the clock comin g into the block before retimin g the data. device version ( dv ) dv-1. device version re p ort the device version re g ister, 0x16, reports the device version as 0x02. ber theoretical actual 10 C3 125 0.25 10 C4 12500 2.5 10 C5 1250000 25 10 C6 1.25e+8 250 10 C7 1.25e+10 2500 10 C8 1.25e+12 2.5e+4 10 C9 1.25e+14 2.5e+5 10 C10 1.25e+16 2.5e+6
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved august 5, 1999 ay99-027sont-2 (replaces ay99-027sont and must accompany ds99-068sont) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 3 of the device august 5, 1999 ay99-027sont-2 re p laces ay99-027sont to incor p orate the followin g u p dates added issues ra-5 and ei-3 to the document.
tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 4 of the device advisory, rev. 2 august 5, 1999 re g ister architecture ( ra ) ma p ra-1. reset bit the software reset bit (bit 0) of register 0x00 is not functional. ra-2. transmit path ais insert bit the txpaisins bit (bit 5) of register 0x01 produces both ais-p and ais-l. ra-3. sts-1 loss of pointer mask bit the sts1lopmsk bit (bit 2) of register 0x04 masks both sts1lop and sts1lof. ra-4. sts-1 loss of frame mask bit the sts1lofmsk bit (bit 1) of register 0x04 is not functional. ra-5. vtlabcom and vtrfirdicom interru p t bits occasionally, it might require multiple reads to clear the composite interrupt bits vtlabcom (bit 2 of register 0x05) and vtrfirdicom (bit 4 of register 0x05). error insertion ( ei ) ei-1. ds1/e1 alarm indication si g nal the device does not insert ds1/e1 ais towards the sts-1 if there is an loc condition in the incoming ds1/e1 signal. ei-2. loc condition in e1 loo p back mode in the absence of an input clock, the device detects an loc condition and generates tu-ais upstream, even if the loopback is selected (the loopback signal is overwritten by tu-ais).
tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 4 of the device august 5, 1999 2 lucent technologies inc. error insertion ( ei ) ( continued ) ei-3. false s-bip, l-bip, and p-bip error insertion the device transmits s-bip, l-bip, and p-bip errors when confi g ured for automatic insertion of rei, and certain sts-1 error conditions such as los, lof, lop-p, s-bip, l-bip, and p-bip are inserted. vt ma pp in g ( vt ) vt-1. vt path pa y load label mismatch the device reports plm-v when it detects three consecutive consistent new values for the vt label. this is in com- pliance with g.783 section 2.2.2.7 and t1.231 section 8.1.3.5.2.4.2 specifications, but is not compliant with gr-253 section 6.2.1.1.8.c. vt-2. failure in the detection of vt loss of pointer defects n the device fails to detect an lop-v defect or insert the re q uired ds1/e1 ais downstream when it receives vt pointer words with the n bits continuousl y set to 1001 ( i.e., with a continuousl y set ndf ) . n the device also apparentl y fails to detect an lop-v defect when it continuousl y receives a vt pointer word of 6c68 ( i.e., a value indicatin g a vt1.5 with an offset of 104 b y tes, versus a maximum valid offset of 103 b y tes ) . in this case, the device inserts the re q uired ds1 ais downstream, but does not subse q uentl y declare an lop-v failure ( nonconformance to gr 253, r6-71 ) . vt-3. ina pp ro p riate termination of vt loss of pointer defect condition after the device has detected an lop-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer. accordin g to gr 253, an lop-v defect must not be terminated unless a valid pointer is received in three consecutive vt superframes ( nonconformance to gr 253, r6-75 ) . vt-4. ina pp ro p riate termination of vt alarm indication si g nal defect condition after the device has detected an ais-v defect, it inappropriatel y terminates that defect upon receivin g two pointer words containin g the same value as the previous valid pointer and without a set ndf ( e. g ., with the n bits set to 0110 ) . accordin g to gr 253, an ais-v defect must not be terminated unless a normal valid pointer is received in three consecutive vt superframes, or a valid pointer with a set ndf is received in one vt superframe ( nonconfor- mance to gr 253, r6-183 ) .
advisory, rev. 2 tmpr28051 sts-1/au-3 (stm-0) mapper august 5, 1999 device advisory for version 4 of the device 3 lucent technologies inc. vt ma pp in g ( vt ) ( continued ) vt-5. c-bit decodin g in the presence of a receive sonet/sdh bit error rate, the device ma y destuff the ds1 from the vt1.5 incorrectl y . this is the result of an error in the vt1.5 c-bit decodin g process. the c-bit decodin g process should be capable of correctin g sin g le errors to the c bits. because of this error, an error in the first or second c bit for position 2 will be incorrectl y decoded if the first c-bit position is callin g for a stuff and the second c-bit position is not. the end result of this error is that both positions will call for a stuff, resultin g in a bit bein g removed from the ds1 data stream. this will force downstream e q uipment to experience a reframe. the minimum time to false decode severit y is as shown in table vt-5 ( in terms of seconds to false decode ) . table vt-5. minimum time ( in seconds ) to false decode severit y of the c bit in the absence of an external bit error rate, the al g orithm decodes these c bits correctl y . device version ( dv ) dv-1. device version re p ort the device version re g ister, 0x16, reports the device version as 0x03. ay99-028sont-2 re p laces ay99-028sont to incor p orate the followin g u p dates added issues ra-5 and e1-3 to the document. ber theoretical actual 10 C3 125 0.25 10 C4 12500 2.5 10 C5 1250000 25 10 C6 1.25e+8 250 10 C7 1.25e+10 2500 10 C8 1.25e+12 2.5e+4 10 C9 1.25e+14 2.5e+5 10 C10 1.25e+16 2.5e+6
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved august 5, 1999 ay99-028sont-2 (replaces ay99-028sont and must accompany ds99-068sont) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) tmpr28051 sts-1/au-3 (stm-0) mapper advisory, rev. 2 device advisory for version 4 of the device august 5, 1999
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper features n maps signals in one of the following ways: maps up to 28 asynchronous ds1 signals to sonet sts-1 via vt groups, or sdh au-3 via tug-2. maps up to 21 asynchronous e1 signals to sdh au-3 via tug-2, or sonet sts-1 via vt groups. maps any valid combination of ds1/e1 signals at the vt group/tug-2 level. n pll-free receive operation using built-in digital jit- ter attenuators. n high-speed microprocessor interface configurable to operate with most commercial microprocessors. n inserts valid b1, b2, and b3 bit interleaved parity (bip) in the transmit direction. n detects and counts b1, b2, and b3 bip-8 errors on either a bit or block basis for performance monitor- ing in the receive direction. n detects and counts v5 bip-2 errors on either a bit or block basis for performance monitoring. n configurable continuous b1, b2, b3, and v5 bip-2 error insertion. n configurable remote error indication (rei) inser- tion for b2, b3, and v5 bip-2 errors. n detects and counts remote errors. n built-in test pattern insertion and drop for setup and maintenance. n configurable vt1.5/tu-11 slot selection for ds1 insertion and drop. n configurable vt2/tu-12 slot selection for e1 insertion and drop. n detects sts-1 path loss of pointer (lop-p), loss of h4 multiframe (h4lomf), path alarm indication signal (ais-p), and path remote defect indication (rdi-p). n automatic receive monitor functions include vt/tu remote defect indication (rdi-v), vt/tu remote error indication (rei-v), bip-2 errors, vt/tu ais (ais-v), and vt/tu loss of pointer (lop-v). n automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a polled mode. n user configurable for vt/tu label, ais-v, rdi-v, rei-v, force bip-2 errors, or unequipped tributary insertion. n typical 3.3 v operation with 5 v ttl tolerant i/o and boundary scan. n C40 c to +85 c temperature range. n 208-pin shrink quad flat pack (sqfp) package. n provides alarm and control features to easily implement the latest release of the following stan- dards: gr253-core (12/97 with the exception of gr-253 section 6.2.1.1.8.c), g.707 (3/96), g.783 (1/94), g.823.393, t1.105-1995, t1.105.02-1995, t1.105.03-1994, t1.105.03a-1995, t1.105.07-1996, t1.105.09-1996, ets300.147 (1/95), ets300.417-1-1 (1/96). a pp lications n sonet/sdh path termination multiplexers n sonet/sdh add/drop multiplexers n sonet/sdh cross connects n digital access cross connects n ds1/e1 broadcast n sonet/sdh test equipment descri p tion the lucent technologies microelectronics group tmpr28051 device is designed to map any valid combination of ds1 and e1 signals into a stream at a rate of 51.84 mbits/s. this device provides all of the functions necessary to insert and drop any valid com- bination up to 28 asynchronous ds1 signals or 21 asynchronous e1 signals into an spe.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 2 lucent technologies inc. table of contents contents pa g e features ...................................................................................................................... ............................................. 1 applications .................................................................................................................. ............................................ 1 description ................................................................................................................... ............................................. 1 block dia g ram ........................................................................................................................... ...............................5 pin information ............................................................................................................... .......................................... 6 nomenclature assumptions ...................................................................................................... ..............................10 ds1/e1 to sts-1 block descriptions ............................................................................................ .........................10 loc and ais monitor ........................................................................................................... ..............................10 ds1/e1 loopback select lo g ic .......................................................................................................................... 10 input select lo g ic ............................................................................................................................ ...................10 elastic store ................................................................................................................. ......................................11 vt generate ................................................................................................................... ....................................11 sts-1/au-3 generate ........................................................................................................... .............................13 spe insertion lo g ic ............................................................................................................................ ................14 sts-1 to ds1/e1 block descriptions ............................................................................................ .........................16 loopback select lo g ic ............................................................................................................................ ...........16 spe locate .................................................................................................................... .....................................16 sts-1/au-3 terminate .......................................................................................................... .............................16 spe drop lo g ic ............................................................................................................................ ......................17 vt terminate .................................................................................................................. ....................................17 jitter attenuate .............................................................................................................. .....................................18 drop select lo g ic ............................................................................................................................ ...................18 test pattern block descriptions ............................................................................................... .............................. 19 test pattern insert ........................................................................................................... ...................................19 test pattern drop ............................................................................................................. ..................................19 microprocessor interface description .......................................................................................... ...........................20 overview ...................................................................................................................... .......................................20 microprocessor confi g uration modes ................................................................................................................. 20 microprocessor interface pins ................................................................................................. ........................... 21 re g ister architecture map ........................................................................................................ ..........................23 re g ister architecture description ................................................................................................ .......................37 i/o timin g .............................................................................................................................. .............................60 absolute maximum ratin g s ............................................................................................................................. .......65 handlin g precautions .................................................................................................................. ...........................65 operatin g conditions ................................................................................................................... ...........................66 electrical characteristics .................................................................................................... ....................................66 timin g characteristics .............................................................................................................. ..............................67 operational timin g .............................................................................................................................. ...............67 transmit s y nc timin g .............................................................................................................................. ...........70 receive s y nc timin g .............................................................................................................................. ............71 t y pical uses .................................................................................................................... .......................................72 path termination multiplex .................................................................................................... .............................72 di g ital cross connect ............................................................................................................ .............................72 test pattern usecomplete s y stem .................................................................................................................73 test pattern useend to end ................................................................................................... ........................ 73 outline dia g ram ........................................................................................................................... ...........................74 208-pin sqfp .................................................................................................................. ..................................74 orderin g information .................................................................................................................. .............................75 ds99-068sont replaces ds98-100tic to incorporate the followin g updates ...................................................75
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 3 lucent technologies inc. list of fi g ures fi g ures pa g e fi g ure 1. block dia g ram ........................................................................................................................... ................5 fi g ure 2. pin dia g ram of 208-pin sqfp ........................................................................................................... .......6 fi g ure 3. mode 1read c y cle timin g ( mpmode = 0, mpmux = 0 ) ...................................................................61 fi g ure 4. mode 1write c y cle timin g ( mpmode = 0, mpmux = 0 ) ...................................................................61 fi g ure 5. mode 2read c y cle timin g ( mpmode = 0, mpmux = 1 ) ...................................................................62 fi g ure 6. mode 2write c y cle timin g ( mpmode = 0, mpmux = 1 ) ...................................................................62 fi g ure 7. mode 3read c y cle timin g ( mpmode = 1, mpmux = 0 ) ...................................................................63 fi g ure 8. mode 3write c y cle timin g ( mpmode = 1, mpmux = 0 ) ...................................................................63 fi g ure 9. mode 4read c y cle timin g ( mpmode = 1, mpmux = 1 ) ...................................................................64 fi g ure 10. mode 4write c y cle timin g ( mpmode = 1, mpmux = 1 ) .................................................................64 fi g ure 11. interface data timin g ............................................................................................................................68 fi g ure 12. serial mode transmit s y nc timin g .......................................................................................................70 fi g ure 13. bus mode transmit s y nc timin g ..........................................................................................................70 fi g ure 14. nonbus parallel mode transmit s y nc timin g .......................................................................................71 fi g ure 15. bus parallel mode receive s y nc timin g ..............................................................................................71 fi g ure 16. sdh/sonet path termination multiplex application ...................................................................... .....72 fi g ure 17. di g ital cross connect application ................................................................................................ .........72 fi g ure 18. test pattern usa g e for complete s y stem ............................................................................................73 fi g ure 19. test pattern usa g e for end-to-end operation ......................................................................................73
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 4 lucent technologies inc. list of tables tables pa g e table 1. pin descriptions ..................................................................................................... .................................... 7 table 2. vt1.5 overhead b y te format ( v5 ) .......................................................................................................... 11 table 3. rfi-v, rdi-v description ............................................................................................. ........................... 11 table 4. vt1.5 superframe ..................................................................................................... .............................. 12 table 5. vt2 superframe ....................................................................................................... ............................... 12 table 6. sts-1 overhead b y te allocation ............................................................................................................. 13 table 7. g1 path condition/performance b y te format ......................................................................................... 13 table 8. vt1.5 spe insertion format ........................................................................................... ......................... 15 table 9. mappin g of vt1.5 # to ( vt group #, vt # ) .............................................................................................. 15 table 10. vt2 spe insertion format ............................................................................................ ......................... 15 table 11. mappin g of vt2 # to ( vt group #, vt # ) ............................................................................................... 15 table 12. microprocessor confi g uration modes .................................................................................................... 20 table 13. mode [ 14 ] microprocessor pin definitions ......................................................................................... 21 table 14. device re g ister map ..................................................................................................................... ........ 23 table 15. re g isters 0x000x16: device-level control, alarm, and mask bits .................................................... 37 table 16. re g isters 0x170x32: ds1/e1 insertion selection ............................................................................. 47 table 17. ds1/e1 insertion selection format ................................................................................... .................... 49 table 18. re g isters 0x330x4e: vt drop selection ........................................................................................... .49 table 19. vt drop selection format ............................................................................................ ......................... 50 table 20. vt to address mappin g ......................................................................................................................... 50 table 21. re g isters 0x4f0x6a: tx vt overhead insertion control ................................................................... 51 table 22. re g isters 0x6b0x86: rx vt drop monitorin g .................................................................................... 52 table 23. re g isters 0x880x89: si g nal override control .................................................................................... 53 table 24. re g isters 0x8a0x8f: di g ital jitter attenuator controls ...................................................................... 54 table 25. re g ister 0x91: sts-1 los detect/test pattern ed g e control .............................................................. 55 table 26. re g ister 0xbf: block control ..................................................................................................... ........... 56 table 27. re g isters 0xc00xfd: detected bip errors ........................................................................................ 5 7 table 28. re g isters 0xfe, 0xff: received sonet/sdh pointer value .............................................................. 57 table 29. re g isters 0xc00xfd: detected rei errors ........................................................................................ 5 8 table 30. re g isters 0xfe0xff: reserved .................................................................................................... ..... 58 table 31. re g isters 0xc00xff: receive j1 path trace b y tes .......................................................................... 59 table 32. re g isters 0xc00xff: transmit j1 path trace b y tes ......................................................................... 59 table 33. microprocessor interface i/o timin g specifications .............................................................................. 60 table 34. absolute maximum ratin g s ................................................................................................................... 65 table 35. esd threshold volta g e ......................................................................................................................... 65 table 36. recommended operatin g conditions ................................................................................................... 66 table 37. lo g ic interface characteristics .................................................................................................. ............ 66 table 38. input clock specifications .......................................................................................... ........................... 67 table 39. input timin g specifications ............................................................................................................... ..... 68 table 40. output clock specifications ......................................................................................... .......................... 69 table 41. output timin g specifications ............................................................................................................... .. 69
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 5 lucent technologies inc. descri p tion ( continued ) on the sts-1 side, the device can be confi g ured for either a serial bit stream or an 8-bit parallel bus. this allows the device to drive an oc-1 optical si g nal directl y and also allows for modular g rowth in terminal or add/drop appli- cations. on the ds1/e1 side, the device is desi g ned to interface with the lucent t7698fl3/t7693 quad line transceiver, or e q uivalent, usin g the internal di g ital j itter attenuator buffer for pll-free operation. the tmpr28051 device contains built-in test pattern insertion and drop that allows end-to-end testin g for initial setup or maintenance without the need for external test e q uipment. built-in loopbacks at both the sts-1 and ds1/ e1 sides provide maximum flexibilit y for use in a number of sonet/sdh or ds1/e1 products includin g terminal multiplexers, add/drop multiplexers, and di g ital cross connects. a hi g h-speed microprocessor interface and full user pro g rammabilit y for vt slot insertion and drop provide maximum flexibilit y for ds1/e1 i/o confi g uration. block dia g ram the block dia g ram is shown in fi g ure 1. for illustration purposes, onl y two of the ds1/e1 bidirectional blocks are shown. 5-4875(f).ar.10 note: n represents 28 or 21 for ds1 or e1, respectivel y . fi g ure 1. block dia g ram microprocessor interface sts-1/au-3 terminate ds1/e1 #1 in elastic store spe insertion logic vt generate elastic store vt generate ds1/e1 #n in sts-1/au-3 generate ds1/e1 #1 out spe drop logic vt terminate vt terminate ds1/e1 #n out sts-1/au-3 in input select logic loop- select logic input select logic spe locate drop select logic loc and test pattern insert test pattern drop back loop- select logic back drop select logic loop- select logic back sts-1/au-3 out ais monitor loc and ais monitor jitter attenuate jitter attenuate
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 6 lucent technologies inc. pin information 5-4873(f).cr.5 fi g ure 2. pin dia g ram of 208-pin sqfp ict vss tclk19 tdata19 rclk19 rdata19 vdd rdata20 rclk20 tdata20 tclk20 tclk21 vdd tdata21 rclk21 rdata21 rdata22 rclk22 tdata22 tclk22 tclk23 vss tdata23 rclk23 rdata23 rdata24 vdd rclk24 tdata24 tclk24 tclk25 vss tdata25 rclk25 rdata25 vdd rdata26 rclk26 tdata26 tclk26 vdd tclk27 tdata27 rclk27 rdata27 vdd rdata28 rclk28 tdata28 tclk28 reset vss vss vss tclk10 tdata10 rclk10 rdata10 rdata9 rclk9 tdata9 tclk9 tclk8 vdd tdata8 rclk8 rdata8 rdata7 rclk7 tdata7 tclk7 tclk6 vss tdata6 rclk6 rdata6 rdata5 vdd rclk5 tdata5 tclk5 tclk4 vss tdata4 rclk4 rdata4 rdata3 rclk3 tdata3 tclk3 tclk2 vdd tdata2 rclk2 rdata2 rdata1 rclk1 tdata1 tclk1 ad7 ad6 ad5 vss vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 e1blueclk vss tclk11 tdata11 rclk11 rdata11 rdata12 rclk12 tdata12 tclk12 tclk13 tdata13 vdd rclk13 rdata13 rdata14 rclk14 tdata14 tclk14 tdo trst vss tms tdi tck rdy_dtack vss rd _r/w mpmode mpmux ale_as vss wr _ds tclk15 tdata15 rclk15 rdata15 rdata16 rclk16 tdata16 vdd tclk16 tclk17 tdata17 rclk17 rdata17 rdata18 rclk18 tdata18 tclk18 vss vss vss vss ad4 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 vdd a2 a1 a0 vdd rsts1par rsts1data0 rsts1data1 rsts1data2 vss rsts1data3 rsts1data4 rsts1data5 rsts1data6 vss rsts1data7 vss rsts1clk vdd vss rsts1serial int cs tsts1clkout tsts1clkin tsts1sync tsts1serial/tsts1data7 tsts1data6 vdd tsts1data5 tsts1data4 tsts1data3 tsts1data2 tsts1data1 tsts1data0 tsts1par ds1blueclk ds1_e1n vss vdd 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 7 lucent technologies inc. pin information ( continued ) table 1. pin descri p tions * i u indicates an internal pull-up; i d indicates an internal pull-down. all i/o not explicitl y stated with a buffer t y pe are 5 v ttl compatible; the y will tolerate 5 v at their inputs. pin s y mbol t yp e* name/descri p tion 47, 39, 38, 30, 29, 20, 19, 11, 10, 3, 206, 199, 198, 190, 175, 167, 166, 159, 154, 146, 145, 137, 136, 127, 126, 117, 115, 107 tclk [ 1:28 ] o transmit ds1/e1 clock. ds1/e1 clock output. e1 si g nals can onl y occup y tclk [ 1:21 ] . 46, 41, 37, 32, 28, 22, 18, 13, 9, 4, 205, 200, 197, 191, 174, 169, 165, 160, 153, 147, 143, 138, 134, 128, 124, 118, 114, 108 tdata [ 1:28 ] o transmit ds1/e1 data. transmit data output. e1 si g nals can onl y occup y tdata [ 1:21 ] . 45, 42, 36, 33, 27, 23, 17, 14, 8, 5, 204, 201, 195, 192, 173, 170, 164, 161, 152, 148, 142, 139, 133, 129, 123, 119, 113, 109 rclk [ 1:28 ] i u receive ds1/e1 clock. receive clock input. these pins have an internal 20 k w pull-up resistor. e1 si g nals can onl y occup y rclk [ 1:21 ] . 44, 43, 35, 34, 25, 24, 16, 15, 7, 6, 203, 202, 194, 193, 172, 171, 163, 162, 151, 149, 141, 140, 132, 131, 122, 120, 112, 110 rdata [ 1:28 ] i u receive ds1/e1 data. receive data input. these pins have an inter- nal 20 k w pull-up resistor. e1 si g nals can onl y occup y rdata [ 1:21 ] . 102 ds1_e1n i ds1/e1 in p ut identifier. if this pin is pulled hi g h, the device will default to ds1 to sts-1 mode and transmit 0s in the unused overhead b y tes and 00 in the ss bits of h1. if pulled low, the device will default to e1 to au-3 mode and transmit 1s in the unused overhead b y tes and 10 in the ss bits of h1. this default selection can be overridden b y settin g toverride and roverride bits in re g isters 0x88 ( bit 0 ) and 0x89 ( bit 0 ) , respectivel y . the seven vt groups can then be individuall y pro- g rammed to carr y either ds1 ( tvtg-1. . . 7 = 1, rvtg-1. . . 7 = 1 ) or e1 ( tvtg-1. . . 7 = 0, rvtg-1. . . 7 = 0 ) si g nals. 101 ds1blueclk i ds1 blue si g nal clock. in the event of a loss of input ds1 clock or an unprovisioned ds1 output, this clock si g nal is used to g enerate the ds1 blue si g nal ( all 1s ) . this clock must be 1.544 mhz 32 ppm or 16 times this rate when usin g the di g ital j itter attenuator. 208 e1blueclk i e1 blue si g nal clock. in the event of a loss of input e1 clock or an unprovisioned e1 output, this clock si g nal is used to g enerate the e1 blue si g nal ( all 1s ) . this clock must be 2.048 mhz 50 ppm or 16 times this rate when usin g the di g ital j itter attenuator.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 8 lucent technologies inc. pin information ( continued ) table 1. pin descri p tions ( continued ) * i u indicates an internal pull-up; i d indicates an internal pull-down. all i/o not explicitl y stated with a buffer t y pe are 5 v ttl compatible; the y will tolerate 5 v at their inputs. pin s y mbol t yp e* name/descri p tion 179 mpmux i micro p rocessor multi p lex mode. settin g mpmux = 1 allows the micropro- cessor interface to accept the multiplexed address and data si g nals. settin g mpmux = 0 allows the microprocessor interface to accept demultiplexed ( separate ) address and data si g nals. 180 mpmode i micro p rocessor mode. when mpmode = 1, the device uses the address latch enable t y pe microprocessor read/write protocol with separate read and write controls. settin g mpmode = 0 allows the device to use the address strobe t y pe microprocessor read/write protocol with a separate data strobe and a combined read/write control. 181 rd _r/w i read ( active-low ) . if mpmode = 1, this pin is asserted low b y the micropro- cessor to initiate a read c y cle. read/write. if mpmode = 0, this pin is asserted hi g h b y the microprocessor to indicate a read c y cle or asserted low to indicate a write c y cle. 178 ale_as i address latch enable. if mpmode = 1, this pin becomes the address latch enable for the microprocessor. when this pin transitions from hi g h to low, the address bus inputs are latched into the internal re g isters. address strobe ( active-low ) . if mpmode = 0, this pin becomes the address strobe for the microprocessor. when this pin transitions from hi g h to low, the address bus inputs are latched into the internal re g isters. 87 cs i u chi p select ( active-low ) . this pin is asserted low b y the microprocessor to enable the microprocessor interface ( see microprocessor confi g uration modes section on pa g e20 ) . this pin has an internal 100 k w pull-up resistor. 86 int o interru p t. this pin is asserted hi g h to indicate an interrupt produced b y an alarm condition in re g ister 3 or 5. the activation of this pin can be masked b y microprocessor re g isters 4 and 6. 183 rdy_dtack o read y . if mpmode = 1, this pin is asserted hi g h to indicate the device has completed a read or write operation. this pin is in a hi g h-impedance state when cs is hi g h. data transfer acknowled g e ( active-low ) . if mpmode = 0, this pin is asserted low to indicate the device has completed a read or write operation. 4850, 5559 ad [ 7:0 ] i/o micro p rocessor interface address/data bus. if mpmux = 0, these pins become the bidirectional, 3-statable data bus. if mpmux = 1, these pins become the multiplexed address/data bus. 6064, 6668 a [ 7:0 ] i micro p rocessor interface address. if mpmux = 0, these pins become the address bus for the microprocessor interface re g isters. 176 wr _ds i write ( active-low ) . if mpmode = 1, this pin is asserted low b y the micro- processor to initiate a write c y cle. data strobe ( active-low ) . if mpmode = 0, this pin becomes the data strobe for the microprocessor. when r/w = 0 ( write ) , a low applied to this pin latches the si g nal on the data bus into internal re g isters. 106 reset i u hardware reset ( active-low ) . if reset is forced low, all internal states in the transceiver paths are reset and data flow throu g h each channel will be interrupted ( see device-level control, alarm, and mask bits ( 0x000x16 ) section on pa g e37 ) . this pin has an internal 20 k w pull-up resistor. 184 tck i u boundar y -scan clock. this pin has an internal 20 k w pull-up resistor.
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 9 lucent technologies inc. pin information ( continued ) table 1. pin descri p tions ( continued ) * i u indicates an internal pull-up; i d indicates an internal pull-down. all i/o not explicitl y stated with a buffer t y pe are 5 v ttl compatible; the y will tolerate 5 v at their inputs. pin s y mbol t yp e* name/descri p tion 185 tdi i u boundar y -scan in p ut data. this pin has an internal 20 k w pull-up resistor. 186 tms i u boundar y -scan mode select. this pin has an internal 20 k w pull-up resistor. 188 trst i d boundar y -scan reset ( active-low ) . this pin has an internal 20 k w pull-down resistor. 189 tdo o boundar y -scan out p ut data. 89 tsts1clkin i transmit sts-1 clock. the sts-1 clock can be 51.84 mhz for serial input data, or 19.44 mhz or 6.48 mhz for b y te-wide data. 90 tsts1sync i transmit sts-1 s y nc. the sts-1 s y nc pulse can be either j0 for 8 khz onl y or a composite of j0j1v1 for 2 khz. 92, 9499 tsts1data [ 6:0 ] o transmit sts-1 data. in the b y te-wide output mode, this is bit 6bit 0 of the data bus. tsts1data7 is the most si g nificant bit of the output b y te. 100 tsts1par o transmit sts-1 parit y . the parit y output is onl y defined for b y te-wide data. the device can be provisioned to source either an odd or even parit y . 91 tsts1serial/ tsts1data7 o transmit sts-1 serial data/transmit sts-1 data bit 7 ( msb ) . in serial mode, this pin provides 51.84 mbits/s serial data. in parallel mode, this pin provides tsts1data7. 88 tsts1clkout o transmit sts-1 out p ut clock. 82 rsts1clk i receive sts-1 clock. the sts-1 clock can be 51.84 mhz for serial input data, or 19.44 mhz or 6.48 mhz for b y te-wide data. 80, 7875, 7371 rsts1data [ 7:0 ] i u receive sts-1 data. in the b y te-wide input mode, this is the data bus with rsts1data7 as the most si g nificant bit of the input b y te. this pin has an internal 100 k w pull-up resistor. 70 rsts1par i u receive sts-1 parit y . the parit y input is onl y defined for b y te-wide data. the device can be provisioned to accept either an odd or even parit y . this pin has an internal 100 k w pull-up resistor. 85 rsts1serial i receive sts-1 serial data. if the device is operatin g in the serial mode, then rsts1serial is used as the input data pin. in the bus mode, this pin is used to s y nchronize b y te 1 of 3 ( see fi g ure 15, pa g e 71 ) . 156 ict i u in-circuit test control ( active-low ) . if ict is forced low, all output pins are placed in the hi g h-impedance state. this pin has an internal 20 k w pull-up resistor. 1, 2, 21, 31, 51, 53, 54, 74, 79, 81, 84, 103, 105, 125, 135, 155, 157, 158, 177, 182, 187, 207 v ss i ground reference for di g ital circuitr y . 12, 26, 40, 52, 65, 69, 83, 93, 104, 111, 116, 121, 130, 144, 150, 168, 196 v dd i power su pp l y for di g ital circuitr y .
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 10 lucent technologies inc. nomenclature assum p tions the mappin g methods ( vt1.5, vt2, and vt group in ansi nomenclature; tu-11, tu-12, and tug-2 in itu nomenclature ) are analo g ous, and for the rest of this document will be referred to as vt1.5, vt2, or vt group. sts-1 and au-3 are also analo g ous with a few minor differences. for the remainder of this document, the 51.84 mbits/s si g nals are referred to as sts-1. ds1/e1 to sts-1 block descri p tions in the descriptions of the block dia g ram of fi g ure 1, some of the control bits exist for each of the ds1/e1 or vt si g nals. upon start-up, the device will set all of the input data t y pes ( ds1 or e1 ) based on the level of the ds1_e1n pin ( pin 102 ) . ds1_e1n controls the value transmitted in the unused overhead b y tes and the value of the transmitted spare bits ( ss ) in the h1 b y te. if this pin is hi g h, then all of the vt groups are populated with ds1 si g nals. if this pin is low, then all of the vt groups are populated with e1 si g nals. this default selection can be overridden b y settin g toverride and roverride bits in re g isters 0x88 ( bit 0 ) and 0x89 ( bit 0 ) , respectivel y . the seven vt groups can then be individuall y pro g rammed to carr y either ds1 ( tvtg-1 . . . 7 = 1, rvtg-1 . . . 7 = 1 ) or e1 ( tvtg-1 . . . 7 = 0, rvtg-1 . . . 7 = 0 ) si g nals. loc and ais monitor the incomin g ds1/e1 si g nal is first checked for loss of clock ( loc ) . loc is reported to the microprocessor via the ds1/e1loc [ 1:21 ] and ds1loc [ 22:28 ] bit ( loc = 1, 0 otherwise ) in re g isters 0x170x32 ( bit 6 ) and also via the aisloccom composite bit in re g ister 0x05 ( bit 1 ) . if loc is present, the device inserts ds1/ e1 ais towards the sts-1 usin g the blue si g nal clock. the incomin g ds1/e1 data ( rdata [ 28:1 ]) is retimed immediatel y b y the associated ds1/e1 clock ( rclk [ 28:1 ]) . the ed g e of the clock that is used to retime the data is user-provisionable at the device level to either the risin g ed g e ( rxds1edge = 1 ) in re g ister 0x02 ( bit 1 ) or fallin g ed g e ( rxds1edge = 0 ) in re g is- ter 0x02 ( bit 1 ) . after bein g retimed, the incomin g data stream is checked for ais. the device will declare ais if the input data is at lo g ic 1 for 3 ms. the device will withstand up to ei g ht errors in the 3 ms period. ais is reported to the microprocessor via the aisloccom composite bit in re g ister 0x05 ( bit 1 ) and the individual ds1/e1ais [ 1:21 ] and ds1ais [ 22:28 ] bits in re g isters 0x170x32 ( bit 7 ) . the blue si g nal clock input si g nal to the device can be at the exact ds1/e1 rate ( 1.544/2.048 mhz ) or at 16 times the ds1/e1 rate ( 24.704/32.768 mhz ) , with a tol- erance of 32 ppm or 50 ppm for ds1 or e1, respec- tivel y . this allows users of the lucent technolo g ies t7698fl3/t7693 devices to reuse the xclk on the board. the tmpr28051 is provisioned to accept the exact ds1 rate b y default ( blueclksel = 0 in bit 2 of re g ister 0x00 ) , but can be chan g ed to perform the divide-b y -16 function ( blueclksel = 1 in bit 2 of re g - ister 0x00 ) . the dut y c y cle of the clock can be 45%/ 55% because the data is retimed internall y in the device. the dut y c y cle re q uires a much ti g hter toler- ance when used for xclk as described earlier. ds1/e1 loo p back select lo g ic the first sta g e after retimin g the si g nal into the device is selection of the externall y received ds1/e1 ( ds1/e1lb [ 1:21 ] or ds1lb [ 22:28 ] = 0 ) or the looped back ds1/e1 ( ds1/e1lb [ 1:21 ] or ds1lb [ 22:28 ] = 1 ) . this selection is provisionable per ds1/e1 input in re g - isters 0x170x32 ( bit 5 ) . in p ut select lo g ic once the ds1/e1 data sources have been selected, the ds1/e1 for each vt tributar y is selected. this selection re q uires 5 bits per slot to determine which ds1/e1 input to use b y provisionin g ds1/e1ins [ 4:0 ] _ [ 1:21 ] or ds1ins [ 4:0 ] _ [ 22:28 ] bits in re g isters 0x170x32 ( bits 4 throu g h 0 ) . the ran g e [ 1:28 ] followin g the _ refers to the tar g et vt #. refer to table 8 on pa g e 15 and table 10 on pa g e 15 for details on the vt locations within the spe. the numberin g scheme for the five provisioned bits ran g es from 00001 to 11100 where the binar y value of the 5 bits corresponds to the ds1/e1 input. for instance, the value 00001 corresponds to selectin g ds1/e1 #1. the unused value of 00000 results in vt une q uipped bein g transmitted. this is the default value for all the vt slots at powerup. vt une q uipped has a valid pointer and all-zero pa y load. the unused values of 11101 11110 will cause ais-v to be inserted for that vt slot.
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 11 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) in p ut select lo g ic ( continued ) the value of 11111 will cause the internall y g enerated test pattern to be inserted for that vt slot. there are no restrictions on the number of vt slots that an y g iven ds1/e1 input can suppl y ( e. g ., up to 28 vt1.5 slots can select the same ds1 input ) . this block can also be used to insert the test pattern ( see test pattern insert section on pa g e19 ) . elastic store the selected ds1/e1 clock and data si g nals are fed to an elastic store that is used to s y nchronize the incom- in g ds1/e1 to the local sts-1 clock. this block deter- mines the need for positive/zero/ne g ative ( p/z/n ) stuffin g for each input. data that is transmitted from this block is s y nchronized to the local transmit sts-1 clock ( tsts1clk ) . this block allows the device to accept ds1 si g nals at 1.544 mbits/s 130 ppm with up to 5 unit intervals peak j itter, or e1 si g nals at 2.048 mbits/s 130 ppm with up to 5 unit intervals peak j itter. vt generate this block g enerates the vt superframe. unless ais-v is bein g forced, the superframe is built with a fixed out- put pointer value of decimal 78 in all the vt1.5 slots. the vt size field is set to 11 binar y , and the new data fla g is set to 0110 binar y . this corresponds to 0x6c4e for the v1 and v2 b y tes within the vt1.5 superframe. also, unless ais-v is bein g forced, the superframe is built with a fixed output pointer value of decimal 105 in all the vt2 slots. the vt size field is set to 10 binar y , and the new data fla g is set to 0110 binar y . this corre- sponds to 0x6869 for the v1 and v2 b y tes within the vt2 superframe. in this block, the ds1/e1 data is placed into the vt, and the vt overhead is g enerated. the format of the vt overhead b y te, v5, is shown in table 2. table 2. vt1.5 overhead b y te format ( v5 ) each vt can be provisioned to insert ais-v b y assi g n- in g vtaisins [ 1:28 ] = 1 in re g isters 0x4f0x6a ( bit 3 ) . ais-v consists of overwritin g the entire vt pa y load and overhead with ones. rdi-v can be automaticall y inserted b y the device ( vtrfirdien [ 1:28 ] = 1 in re g isters 0x4f0x6a, bit 6 ) or written into the v5 b y te under control of the micro- processor ( vtrfirdien [ 1:28 ] = 0 in re g isters 0x4f0x6a, bit 6 ) . in the automatic mode, the values for bit 4 ( rfi-v ) and bit 8 ( rdi-v ) are defined in table 3. the automatic insertion mode ma y not meet the different standards bod y re q uirements unless the vt pte at both ends of the path ( and an y intermediate nes provisioned to perform intermediate-path pm on that path ) support the protocol defined in table 3. to meet the different standards re q uirements, the micro- processor mode allows pro g rammin g the rdi-v and rfi-v bits in re g isters 0x4f0x6a b y pro g rammin g vtrfiins [ 1:28 ] ( bit 5 ) and vtrdiins [ 1:28 ] ( bit 4 ) , respectivel y . table 3. rfi-v, rdi-v descri p tion the vt label for each vt is also provisionable throu g h the microprocessor b y pro g rammin g the vtlabins [ 2:0 ] _ [ 1:28 ] in re g isters 0x4f0x6a, bit 2 throu g h bit 0. bit #12 3 4 567 8 bip-2 rei-v rfi-v si g nal label rdi-v bit 4 bit 8 descri p tion 0 0 no alarm 0 1 ais-v or lop-v 10vt pa y load mismatch 11vt une q uipped
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 12 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) vt generate ( continued ) in addition to g eneratin g the superframe, this block automaticall y g enerates the bip-2 si g nal. each vt can be confi g ured to intentionall y insert continuous bip-2 errors for troubleshootin g purposes ( bip2erins [ 1:28 ] = 1 in bit 7 of re g isters 0x4f0x6a ) . this bip error insert field forces errors on both bip-2 bits. the resultant vt1.5 and vt2 superframes are shown in table 4 and table 5, where: b y te [ 24/32:1 ] = information bit o = overhead bit r = fixed stuff bit v1, v2, v3 = pointer and pointer action b y tes s1, s2 = stuff opportunit y bits v4 = reserved c1, c2 = stuff indication bits v5 = vt overhead b y te j2, z6/n2, z7/k4 = unused table 4. vt1.5 su p erframe table 5. vt2 su p erframe v1 v5 rrrrrrir b y te 1 : b y te 24 v2 j2 c1c2ooooir b y te 1 : vt1.5 b y te 24 superframe v3 z6/n2 c1c2ooooir b y te 1 : b y te 24 v4 z7/k4 c1c2rrrs1s2r b y te 1 : b y te 24 v1 v5 rrrrrrrr b y te 1 : b y te 32 rrrrrrrr v2 j2 c1c2oooorr b y te 1 : b y te 32 rrrrrrrr vt2 v3 superframe z6/n2 c1c2oooorr b y te 1 : b y te 32 rrrrrrrr v4 z7/k4 c1c2rrrrrs1 s2 b y te 1 [ 6:0 ] : b y te 32 rrrrrrrr
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 13 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) vt generate ( continued ) the device would transmit 0 in each of the o bits when the ds1_e1n pin is pulled hi g h. if ds1_e1n is pulled low, the device will transmit 1 in each of the o bits. the r bits are alwa y s set to 1. the device transmits all 1s in the j2, z6/n2, and z7/k4 b y tes. the device can be confi g ured such that an y detected bip-2 errors in the vt receive side result in rei-v bein g written into the correspondin g transmit vt slot ( when rei_en = 1 in bit 7 of re g ister 0x01 ) . sts-1/au-3 generate the device g enerates an sts-1 si g nal based on an incomin g clock ( tsts1clk ) and frame s y nc pulse ( tsts1sync ) . the frame s y nc pulse can be a sin g le clock-period wide to indicate an 8 khz s y nc, or it can contain pulses in three clock periods to indicate a com- posite 2 khz s y nc. ( see the transmit s y nc timin g sec- tion, pa g e 70. ) the sts-1 frame is 9 rows x 90 columns that repeats at an 8 khz rate. each column is 1-b y te wide. the sts-1 frame contains three columns of transport over- head, one column of path overhead, and 86 columns of pa y load. the 36 b y tes of sts-1 overhead are allocated as shown in table 6. table 6. sts-1 overhead b y te allocation the overhead b y tes that are inserted b y the device are described below. all of the remainin g overhead b y tes are g iven a fixed value of all 0s when ds1_e1n ( bit 0 in re g ister 0x07 ) is hi g h, or all 1s when ds1_e1n is low. the device inserts the correct frame pattern of 0xf628 into the a1 and a2 b y tes. the device inserts a fixed value of 0x01 into the j0 b y te. the device g enerates and inserts valid b1, b2, and b3 bip-8 even parit y b y tes into the sts-1 overhead. these b y tes are forced to odd parit y when b [ 1:3 ] errins = 1 in bit 6 throu g h bit 4 of re g ister 0x00. the device will provide an sts-1 pointer with a fixed value of 522 ( decimal ) with 0110 in the new data fla g ( ndf ) bits. the ss bits are determined b y the level of the ds1_e1n pin. when this pin is hi g h, the device puts 00 in the ss bits. when this pin is low, the device puts 10 in the ss bits. this pointer value indicates that the j1 path overhead b y te follows immediatel y after the j0 line overhead b y te. the j1 b y te is used for path trace. this b y te repetitivel y transmits a 64-b y te fixed len g th se q uence to verif y end-to-end connectivit y . these 64 b y tes are pro g ram- mable b y the microprocessor b y provisionin g tj1byte [ 7:0 ] _ [ 64:1 ] in re g isters 0xc00xff ( when tj1byte = 1 in re g ister 0xbf ) . the method for pro- g rammin g these bits is described in detail in the re g is- ter description of the transmit j1 path trace b y tes, pa g e 59. the f2 b y te can be provisioned b y the microprocessor ( f2ins- [ 7:0 ]) in re g ister 0x10. the device inserts a value of 0x02 into the c2 b y te, indicatin g vt structured sts-1 spe. the three least si g nificant bits of the k2 b y te can be provisioned b y the microprocessor ( k2ins- [ 6:8 ] ) in re g - ister 0x11. the four least si g nificant bits of the s1 b y te can be pro- visioned b y the microprocessor ( s1ins- [ 3:0 ]) in re g is- ter 0x13. the m0 b y te is used to report b2 line rei ( rei-l ) when rei_en = 1 in re g ister 0x01. this re g ister contains the number of b2 bip-8 errors detected in the current receive frame circuitr y when rei_en = 1 ( bit 7 0f re g is- ter 0x01 ) . valid values for these 4 bits are 00001000. the g1 b y te is used to conve y path condition and per- formance back to the far end. the format of the g1 b y te is shown in table 7. table 7. g1 path condition/performance b y te format col. 1 col. 2 col. 3 col. 4 row 1 a1 a2 j0 j1 row 2 b1 e1 f1 b3 row 3 d1 d2 d3 c2 row 4 h1 h2 h3 g1 row 5 b2 k1 k2 f2 row 6 d4 d5 d6 h4 row 7 d7 d8 d9 z3/f3 row 8 d10 d11 d12 z4/k3 row 9 s1 m0 e2 z5/n1 bit #1234 5 678 rei-p user-provisioned rdi-p
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 14 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) sts-1/au-3 generate ( continued ) path remote error indicator ( rei-p ) reports the number of remote errors. the four rei-p bits contain the num- ber of b3 bip-8 errors detected in the current frame when rei_en = 1 ( bit 7 of re g ister 0x01 ) . valid values for these 4 bits are 00001000. the path remote defect indicator ( rdi-p ) bits report back such condi- tions as receive ais-p, si g nal failure, and path trace mismatch. these bits, 5 throu g h 8 of the g1 b y te ( g1ins- [ 5:8 ] in re g ister 0x11 ) , are user pro g rammable b y the microprocessor and are not inserted automati- call y b y the device. the h4 b y te is inserted usin g the reduced h4 codin g se q uence format, where the 6 most si g nificant bits are ones, and the 2 least si g nificant bits take on the follow- in g values: 00-01-10-11-00, etc. the value of 00 indi- cates that the next sts-1 spe contains the v1 overhead b y te. the sts-1 can be provisioned to send ais-p ( txpaisins = 1 in bit 5 of re g ister 0x01 ) . writin g ais-p consists of writin g all 1s into the h1h3 b y tes and the entire spe. the transmitted sts-1 can be confi g ured to scramble the output data ( sts1scr = 1 in bit 2 of re g ister 0x01 ) or transmit the data without scramblin g ( sts1scr = 0 in bit 2, re g ister 0x01 ) . it is useful to turn off sonet scramblin g if the data is g oin g to be immediatel y multi- plexed into a hi g her rate sonet si g nal. when sts1scr = 1 in re g ister 0x01, the device scrambles the out g oin g sts-1 frame accordin g to the sonet frame s y nchronous scramblin g se q uence 1 + x 6 + x 7 . the se q uence is reset to 1111111 at the be g innin g of the b y te followin g the c1 b y te and scrambles all of the sts-1 data except the a1, a2, and c1 b y tes. when this bit is 0, then the transmit data is not scrambled b y the device. spe insertion lo g ic in addition to the one column of path overhead and 84 columns of vt pa y load, the sts-1 spe also contains two columns of fixed stuff b y tes. the path overhead is located in column #1, while column #30 and column #59 contain the fixed stuff b y tes. the remainin g col- umns contain the interleaved vt data as shown in ta b l e 8 . the spe insertion lo g ic block acts in con j unction with the sts-1 frame g enerate block to place the vt infor- mation in the transmitted data stream. the cross-referencin g between the vt1.5 # listed in table 8 and the standard format ( vt group #, vt # ) listed in gr-253-core section 3.2.4 is shown in ta b l e 9 . the cross-referencin g between the vt2 # listed in table 10 and the standard format ( vt group #, vt # ) listed in gr-253-core section 3.2.4 is shown in ta b l e 11 .
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 15 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) spe insertion lo g ic ( continued ) table 8. vt1.5 spe insertion format spe column # 1234567891 0 1 1 2 8 2 9 3 0 3 1 3 2 5 7 5 8 5 9 6 0 6 1 6 2 8 1 8 2 8 3 8 4 8 5 8 6 8 7 p a t h o h v t 1 . 5 # 1 v t 1 . 5 # 2 v t 1 . 5 # 3 v t 1 . 5 # 4 v t 1 . 5 # 5 v t 1 . 5 # 6 v t 1 . 5 # 7 v t 1 . 5 # 8 v t 1 . 5 # 9 v t 1 . 5 # 1 0 ? ? ? v t 1 . 5 # 2 7 v t 1 . 5 # 2 8 f i x e d v t 1 . 5 # 1 v t 1 . 5 # 2 ? ? ? v t 1 . 5 # 2 7 v t 1 . 5 # 2 8 f i x e d v t 1 . 5 # 1 v t 1 . 5 # 2 v t 1 . 5 # 3 ? ? ? v t 1 . 5 # 2 2 v t 1 . 5 # 2 3 v t 1 . 5 # 2 4 v t 1 . 5 # 2 5 v t 1 . 5 # 2 6 v t 1 . 5 # 2 7 v t 1 . 5 # 2 8 table 9. ma pp in g of vt1.5 # to ( vt grou p #, vt # ) vt1.5 # (vt group #, vt #) vt1.5 # (vt group #, vt #) vt1.5 # (vt group #, vt #) vt1.5 # (vt group #, vt #) 1 1, 1 8 1, 2151, 3221, 4 2 2, 1 9 2, 2162, 3232, 4 3 3, 1103, 2173, 3243, 4 4 4, 1 11 4, 2 18 4, 3 25 4, 4 5 5, 1125, 2195, 3265, 4 6 6, 1136, 2206, 3276, 4 7 7, 1147, 2217, 3287, 4 table 10. vt2 spe insertion format spe column # 1234567891 0 1 1 2 8 2 9 3 0 3 1 3 2 5 7 5 8 5 9 6 0 6 1 6 2 8 1 8 2 8 3 8 4 8 5 8 6 8 7 p a t h o h v t 2 # 1 v t 2 # 2 v t 2 # 3 v t 2 # 4 v t 2 # 5 v t 2 # 6 v t 2 # 7 v t 2 # 8 v t 2 # 9 v t 2 # 1 0 ? ? ? v t 2 # 6 v t 2 # 7 f i x e d v t 2 # 8 v t 2 # 9 ? ? ? v t 2 # 1 3 v t 2 # 1 4 f i x e d v t 2 # 1 5 v t 2 # 1 6 v t 2 # 1 7 ? ? ? v t 2 # 1 5 v t 2 # 1 6 v t 2 # 1 7 v t 2 # 1 8 v t 2 # 1 9 v t 2 # 2 0 v t 2 # 2 1 table 11. ma pp in g of vt2 # to ( vt grou p #, vt # ) vt2 # (vt group #, vt #) vt2 # (vt group #, vt #) vt2 # (vt group #, vt #) 1 1, 1 8 1, 2 15 1, 3 2 2, 1 9 2, 2 16 2, 3 3 3, 1103, 2173, 3 4 4, 1 11 4, 2 18 4, 3 5 5, 1125, 2195, 3 6 6, 1136, 2206, 3 7 7, 1147, 2217, 3
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 16 lucent technologies inc. ds1/e1 to sts-1 block descri p tions ( continued ) spe insertion lo g ic ( continued ) the device can transmit the data as either a serial bit stream ( txserial = 1 in re g ister 0x02, bit 6 ) or as a parallel b y te of data ( txserial = 0 in re g ister 0x02, bit 6 ) . there are two parallel modes of operation: bus mode and nonbus mode. bus mode allows multiple tmpr28051 devices to operate on a 19.44 mhz bus; in nonbus mode, the device transmits data in a point-to-point fashion at 6.48 mhz. in either parallel mode, the device sends a parit y bit with the data. this parit y bit is confi g urable to be either odd ( txparity = 1 in re g ister 0x02, bit position 4 ) or even ( txparity = 0 in re g ister 0x02, bit position 4 ) parit y . the bus mode of operation re q uires the device to select which sts-1 time slot of the three that are avail- able to transmit data. the tbusmode bit ( bit 2 ) in re g - ister 0x12 determines whether the device operates in bus mode ( tbusmode = 1 ) or nonbus mode ( tbusmode = 0 ) . b y default, the device powers up in bus mode. the tbuspos bits ( bit 1 and bit 0 ) in re g is- ter 0x12 determine in which of the three time slots the device transmits. b y default, the device does not trans- mit ( tbuspos- [ 1:0 ] = 00 in re g ister 0x12 ) , but it can be confi g ured to transmit durin g an y of the three sts-1 time slots on the 19.44 mhz bus. in all three modes, the device frame s y nc input allows the 8 khz sts-1 frames as well as the 2 khz vt super- frames to be ali g ned. sts-1 to ds1/e1 block descri p tions loo p back select lo g ic the device can be confi g ured to loop back the transmit sts-1 ( sts1lb = 1 in bit 0 of re g ister 0x01 ) or accept the receive sts-1 si g nal ( sts1lb = 0 in bit 0 of re g is- ter 0x01 ) . when the receive sts-1 si g nal is selected, the user can confi g ure which ed g e of the clock to use to retime the data ( rxsts1edge = 1 in bit 3 of re g is- ter 0x02 uses the risin g ed g e; rxsts1edge = 0 in bit 3 of re g ister 0x02 uses the fallin g ed g e ) . spe locate the device can receive data as either a serial bit stream ( rxserial = 1 in bit 7 of re g ister 0x02 ) or as a parallel b y te ( rxserial = 0 in bit 7 of re g ister 0x02 ) . in the parallel mode, the device receives a parit y bit with the data. this bit is confi g urable to odd ( rxparity = 1 in bit 5 of re g ister 0x02 ) or even ( rxparity = 0 in bit 5 of re g ister 0x02 ) parit y . errors in this bit are reported to the microprocessor ( rxparer in bit 6 of re g ister 0x03 ) . the bus mode of operation is similar to normal opera- tion in the ds1/e1 to sts-1 direction. the device defaults to the bus mode ( rbusmode = 1 in bit 5 of re g ister 0x12 ) of operation and listens to none of the receive channels ( rbuspos- [ 1:0 ] = 00 in bit 4 and bit 3 of re g ister 0x12 ) . the s y nc pulse is used onl y to define time slot #1 of the three that are possible. bus mode operation re q uires at least one s y nc pulse to define the time slot. the sts-1 locate block performs the functions neces- sar y to locate the spe. the device will frame on the incomin g sts-1 si g nal, and indicate when it is in the out of frame ( oof ) condition ( sts1oof = 1 in bit 0 of re g ister 0x03 ) or loss of frame ( lof ) condition ( sts1lof = 1 in bit 1 of re g ister 0x03 ) . loss of frame is defined as bein g in the oof condition for 3 ms or more. both the oof and lof are current state condi- tions; the y hold their value for a minimum of 500 m s after the event. the indications reset if the condition is no lon g er true. the device monitors the received data b y tes for contin- uous ones or zeros. if the number of continuous data b y tes exceeds the provisioned value ( losdet- [ 7:0 ] in re g ister 0x91 ) , then loss of si g nal ( sts1los = 1 in bit 0 of re g ister 0x05 ) is declared. if the value in losdet- [ 7:0 ] in re g ister 0x91 is 0x00, then los is not declared. sts-1/au-3 terminate the sts-1 terminate block can descramble the output data ( sts1dscr = 1 in bit 1 of re g ister 0x01 ) or output the received data without descramblin g ( sts1dscr = 0 in bit 1 of re g ister 0x01 ) . it is useful to turn off descramblin g if the data is received locall y from a hi g her-rate si g nal where descramblin g has alread y taken place. for performance monitorin g purposes, there are a number of bip and rei error counters ( re g isters 0xc00xff ) in the receive section of the device. all of these internal counters are comprised of a runnin g error counter and a hold re g ister that presents stable results to the microprocessor. the counts in all of the runnin g counters are latched to the hold re g isters when latch_cnt ( bit 3 ) in re g ister 0x00 is written from 0 to 1. this also resets all of the runnin g counters. the results are then held until read b y the microprocessor.
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 17 lucent technologies inc. sts-1 to ds1/e1 block descri p tions ( continued ) sts-1/au-3 terminate ( continued ) all of the internal counters have the abilit y to store more than one second of counts. as lon g as the latch_cnt ( bit 3 ) in re g ister 0x00 occurs ever y sec- ond or faster, no counts will be lost. in case this does not happen, all of the runnin g counters will hold their maximum value rather than roll over to zeros. the device performs pointer interpretation on the incomin g si g nal to locate the start of the spe. the pointer interpretation block will indicate when the device is in the path loss of pointer ( lop-p ) or path ais ( ais-p ) condition. loss of pointer condition is declared as the result of either of the followin g conditions: 1. continuous ndfif the device receives 1001 in the ndf field for nine consecutive frames, then lop-p is declared. 2. invalid pointer valuesif the device receives nine frames consecutivel y of a pointer that is not a nor- mal value, ndf, ais-p, increment, or decrement, then lop-p is declared. the ss bits do not contrib- ute to lop-p when ds1_e1n is hi g h; otherwise, a non-10 value in the ss bits will contribute to lop-p. ais-p is declared on three consecutive frames with all 1s in the h1 and h2 b y tes. ais-p and lop-p are mutuall y exclusive conditions. if neither sts1pais ( bit 3 in re g ister 0x03 ) or sts1lop ( bit 2 in re g ister 0x03 ) is a lo g ic 1, then the pointer interpreter declares a normal pointer. as part of the normal operation, the device will respond appropriatel y to valid ndf, increment, and decrement indications. increment and decrement operations will be counted b y the device and presented to the microprocessor via the sptr+ [ 7:0 ] and sptrC [ 7:0 ] bits in re g isters 0xfe and 0xff, respectivel y . the b1, b2, and b3 bip-8 values are recalculated and compared to the received values. an y differences are counted b y the appropriate error counter ( b [ 1:3 ] bipcnt- [ 15:0 ] in re g isters 0xc00xc5 when bip_cnts = 1 in re g ister 0xbf ) . in addition, b2 and b3 rei errors are also counted in re g isters 0xc20xc5 ( b [ 2:3 ] rei- [ 15:0 ] ; re g ister 0xbf settin g s: rei_cnts = 1 and bip_cnts = 0 ) . the runnin g and latched counts for both b1 and b2 counters are held at zero durin g oof. the runnin g and latched counts for b3 counters are held at zero durin g oof as well as lop-p. the device can be provisioned to count bits in error ( bipblkcnt = 0 in bit 1 of re g ister 0x00 ) or blocks in error ( bipblkcnt = 1 in bit 0 of re g ister 0x00 ) . the j1 b y te is terminated within the device. this con- sists of writin g the receive j1 se q uentiall y in a 64-b y te re g ister ( modulo 64 ) . at start-up, the receive j1 b y te re g ister is all 0s. when- ever the received j1 b y te value does not match the current j1 b y te in the re g ister, the path trace mismatch traceer bit ( bit 7 in re g ister 0x03 ) is set to lo g ic 1. this allows the user to read the 64-b y te re g ister once, and then i g nore it unless differences are received. traceer bit ( bit 7 in re g ister 0x03 ) is masked durin g ais-p and lop-p. the f2 b y te ( f2- [ 7:0 ] in re g ister 0x0b ) , the c2 b y te ( c2- [ 7:0 ] in re g ister 0x0c ) , the 3 least si g nificant bits of the k2 b y te ( k2- [ 6:8 ] in re g ister 0x0d ) , the 4 least si g - nificant bits of the s1 b y te ( s1- [ 3:0 ] in re g ister 0x14 ) , and the 4 least si g nificant bits of the g1 b y te ( g1- [ 5:8 ] in re g ister 0x0d ) are monitored b y the microprocessor. the number of consistent, consecutive frames to update the values of all of these monitored b y tes can be set b y the user to an y where between 2 and 15 frames ( f2#det- [ 3:0 ] in re g ister 0x0e, c2#det- [ 3:0 ] in re g ister 0x0e, k2#det- [ 3:0 ] in re g ister 0x0f, g1#det- [ 3:0 ] in re g ister 0x0f ) . none of these re g is- ters will update durin g oof condition. spe dro p lo g ic the spe drop lo g ic uses the h4 multiframe indicator to identif y the v1 b y te and drop the data to the correct vt termination blocks. loss of multiframe s y nchronization will be reported to the microprocessor ( h4lomf = 1 in bit 4 of re g ister 0x03 ) . vt terminate the vt terminate block performs vt pointer interpreta- tion on the received si g nal to locate the vt overhead. lop-v ( vtlop [ 1:28 ] bit 6 in re g isters 0x6b0x86 ) and ais-v ( vtais [ 1:28 ] bit 3 in re g isters 0x6b0x86 ) are reported to the microprocessor. lop-v is declared as a result of either of the followin g conditions: 1. continuous ndfif the device receives 1001 in the ndf field for nine consecutive superframes, then lop-v is declared. 2. invalid pointer valuesif the device receives nine frames consecutivel y of a pointer that is not a nor- mal value, ndf, ais-v, increment, or decrement, then lop-v is declared. the ss bits do contribute to lop-v.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 18 lucent technologies inc. sts-1 to ds1/e1 block descri p tions ( continued ) vt terminate ( continued ) ais-v is declared on three consecutive superframes with all 1s in the v1 and v2 b y tes. ais-v and lop-v are mutuall y exclusive conditions. if neither vtais [ 1:28 ] ( bit 3 in re g isters 0x6b0x86 ) or vtlop [ 1:28 ] ( bit 6 in re g isters 0x6b0x86 ) is a lo g ic 1, then the pointer interpreter declares a normal pointer. as part of the normal operation, the device will respond appropriatel y to valid ndf, increment, and decrement indications. increment and decrement oper- ations will be counted b y the device and presented to the microprocessor via bits vt [ 1:28 ] ptr+ [ 3:0 ] in re g is- ters 0xc60xff ( bip_cnts = 1 ) , and via vt [ 1:28 ] ptrC [ 3:0 ] in re g isters 0xc60xff ( rei_cnts = 1 and bip_cnts = 0 ) , respectivel y . mismatches between the expected vt size bits, bit 11 for vt1.5 and bit 10 for vt2, and the actual received ss size bits are reported to the microprocessor vtsizeer [ 1:28 ] bit ( bit 7 in re g isters 0x6b0x86 ) . once the v5 b y te is located, the device checks for received bip-2 errors ( b2bipcnt- [ 15:0 ] in re g isters 0xc00xc1 when bip_cnts bit in re g ister 0xbf is set to 1 ) and received rei ( b [ 2:3 ] rei- [ 15:0 ] in re g isters 0xc20xc5 when rei_cnts and bip_cnts in re g - ister 0xbf are set to a 1 and 0, respectivel y) . in addi- tion to reportin g the occurrence of bip-2 errors and rei, the device also maintains a count of each of these on a per vt basis ( vtrei [ 7:0 ] _ [ 1:28 ] in re g isters 0xc70xfd: rei_cnts = 1, bip_cnts = 0, and bip2cnt [ 7:0 ] _ [ 1:28 ] in re g isters 0xc70xfd: bip_cnts = 1 ) . these runnin g and latched counts for both bip-2 and rei counters are held at zero durin g oof, lop-p, lop-v, and ais-v. additionall y , the device checks for received rfi-v and rdi-v ( bit 5 and bit 4, respectivel y , in re g isters 0x6b0x86 ) and received vt label ( vtlab [ 2:0 ] _ [ 1:28 ] , bit 2 throu g h bit 0 in re g isters 0x6b0x86 ) . whenever the device receives three consecutive consistent values for the vt label fields that are different from the current values, it latches the new value and reports the chan g e to the microproces- sor. when a 1 is received in vtrdi0_ [ 1:28 ] , bit 4 in re g isters 0x6b0x86 ( represents bit 8 of the vt v5 overhead b y te ) , for 10 consecutive superframes, it declares an rdi-v condition. jitter attenuate each of the 28 vts has a built-in di g ital j itter attenuator to remove the effects of mappin g j itter and pointer ad j ustment j itter. the bits in re g isters 0x8a0x8f are used to control various aspects of the di g ital j itter atten- uator. two pro g rammable terms are used to set the 2nd-order loop dampin g factor and natural fre q uenc y of the pll. these terms are the g ain threshold, set b y djagthr [ 23:0 ] in re g isters 0x8d0x8f, and scale value, set b y djascale [ 15:0 ] in re g isters 0x8b0x8c. the pll bandwidth can be set usin g the above re g isters to accommodate various s y stem con- straints. the di g ital j itter attenuator block can be enabled b y settin g the bit djactl = 1 ( bit 4 ) in re g ister 0x01. these di g ital j itter attenuators re q uire a blue si g nal clock that runs at 16 times the nominal output rate. the di g ital j itter attenuators are desi g ned to meet cur- rent j itter specifications as well as maximum time inter- val error ( mtie ) re q uirements. the clock transmitted from this block nominall y has a 50% dut y c y cle. the j it- ter attenuator block can be b y passed b y settin g djactl = 0 ( bit 4 ) in re g ister 0x01. if this block is b y passed, the output produces g apped clock and data. dro p select lo g ic once the vt has been terminated, the source vt for each ds1/e1 output is selected. this selection re q uires 5 bits per slot to determine which vt to use b y pro g rammin g vtdrop [ 4:0 ] _ [ 1:28 ] bits ( bits 4 throu g h 0 in re g isters 0x330x4e ) . the numberin g scheme for the five provisioned bits ran g es from 00001 to 11100, where the binar y value of the 5 bits corresponds to the vt source. for instance, the value 00001 corresponds to selectin g vt group 1, vt #1. the unused values of 00000 and 11101 11110 will cause ais to be inserted for that ds1 output. b y default, all ds1/e1 outputs reset to a value of 00000 on powerup, which causes all of the ds1/e1s to transmit ais ( all 1s ) usin g the blue si g nal clock. the value of 11111 will insert the test pattern as described next.
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 19 lucent technologies inc. test pattern block descri p tions the device contains a test pattern g enerator and a test pattern detector for use in maintenance and trouble- shootin g . test pattern insert the test pattern g enerator is capable of transmittin g four different test patterns ( xmt_pat- [ 1:0 ] in bit posi- tions 0 and 1 of re g ister 0x08 ) . in addition to a 2 15 C 1, a 2 20 C 1, and a 2 23 C 1 se q uence, the device can also transmit a qrss se q uence. the qrss pattern is a 2 20 C 1 pseudorandom bit se q uence defined b y the e q uation 1 + x 17 + x 20 = 0, with a 14 zero limit. as can be seen in fi g ure 1 on pa g e 5, this test pattern can be inserted in the place of an y of the transmitted or received ds1/e1 si g nals. the test pattern can also be provisioned to be framed ( xmt_frame = 1 in bit 2 of re g ister 0x08 ) or unframed ( xmt_frame = 0 in bit 2 of re g ister 0x08 ) . the framed se q uence can be either ds1 sf format ( tp_ds1e1n = 1 in bit 7 of re g ister 0x09 ) or e1 format ( tp_ds1e1n = 0 in bit 7 of re g ister 0x09 ) . the test pattern can also be forced to transmit a bit error ( error_ins bit in re g ister 0x08, bit position 3, is forced to make low to hi g h transition ) . the test patterns are o.151 compliant, so the y can be used to drive external test e q uipment as well as to perform internal maintenance and troubleshootin g . test pattern dro p the test pattern detector can detect the same four test se q uences g enerated b y the test pattern g enerator ( rcv_pat- [ 1:0 ] in bit positions 4 and 5 of re g ister 0x08 ) . when the detector is out of s y nchronization, the device continuousl y monitors the input data si g nal for matches with the expected data si g nal. when the device detects 32 matches in a row, it declares itself in s y nc ( tpoos = 0 in bit 7 of re g ister 0x0a ) , and the error detector is enabled. if the device detects ei g ht consecutive bit mismatches, the test pattern detector declares itself out of s y nc ( tpoos = 1 ) , and starts searchin g a g ain. the test pattern detector can be confi g ured to look for a framed ( rcv_frame = 1 in bit 6 of re g ister 0x08 ) or unframed ( rcv_frame = 0 in bit 6 of re g ister 0x08 ) si g nal. while in s y nc, the device counts the number of times the input data differs from the expected data in a 7-bit counter, tperr- [ 6:0 ] ( bit 0 throu g h bit 6 in re g ister 0x0a ) , that holds its count when it reaches the maxi- mum value of 128. this counter is reset when the latch_tp bit ( bit 7 ) in re g ister 0x08 makes a 0 to 1 transition.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 20 lucent technologies inc. micro p rocessor interface descri p tion overview the device is e q uipped with an as y nchronous microprocessor interface that allows operation with most commer- ciall y available microprocessors. inputs mpmux and mpmode are used to confi g ure this interface into one of four possible modes. the mpmux settin g selects either a multiplexed 8-bit address/data bus ( ad [ 7:0 ]) , or a demulti- plexed 8-bit address bus ( a [ 7:0 ]) and an 8-bit data bus ( ad [ 7:0 ]) . the mpmode settin g selects the associated set of re g isters within the device. the microprocessor interface can operate at speeds up to 33 mhz in interrupt-driven or polled mode without wait-states. to conform to standards, there are a limited number of default powerup or reset states. all read/write re g isters must be written b y the microprocessor on s y stem start-up to g uarantee proper device functionalit y . micro p rocessor confi g uration modes table 12 hi g hli g hts the four microprocessor modes controlled b y the mpmux and mpmode inputs. table 12. micro p rocessor confi g uration modes mode mpmode mpmux address/data bus generic control, data, and out p ut pin names mode 1 0 0 demuxed cs , as , ds , r/w , a [ 7:0 ] , ad [ 7:0 ] , int, dtack mode 2 0 1 muxed cs , as , ds , r/w , ad [ 7:0 ] , int, dtack mode 3 1 0 demuxed cs , ale, rd , wr , a [ 7:0 ] , ad [ 7:0 ] , int, rdy mode 4 1 1 muxed cs , ale, rd , wr , ad [ 7:0 ] , int, rdy
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 21 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) micro p rocessor interface pins the mode [ 14 ] specific pin definitions are g iven in table 13. note that the microprocessor interface uses the same set of pins in all modes. table 13. mode [14] micro p rocessor pin definitions confi g uration device pin name generic pin name pin t yp e assertion sense function mode 1 wr _ds ds input active-low data strobe rd _r/w r/w input read/write r/w = 1 for read r/w = 0 for write ale_as as input address strobe cs cs input active-low chip select int int output active-hi g h interrupt rdy_dtack dtack output active-low data acknowled g e ad [ 7:0 ] ad [ 7:0 ] i/o data bus a [ 7:0 ] a [ 7:0 ] input address bus mode 2 wr _ds ds input active-low data strobe rd _r/w r/w input read/write r/w = 1 for read r/w = 0 for write ale_as as input address strobe cs cs input active-low chip select int int output active-hi g h interrupt rdy_dtack dtack output active-low data acknowled g e ad [ 7:0 ] ad [ 7:0 ] i/o address/data bus
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 22 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) micro p rocessor interface pins ( continued ) table 13. mode [14] micro p rocessor pin definitions ( continued ) confi g uration device pin name generic pin name pin t yp e assertion sense function mode 3 wr _ds wr input active-low write rd _r/w rd input read ale_as ale input address latch enable cs cs input active-low chip select int int output active-hi g h interrupt rdy_dtack rdy output active-low read y ad [ 7:0 ] ad [ 7:0 ] i/o data bus a [ 7:0 ] a [ 7:0 ] input address bus mode 4 wr _ds wr input active-low write rd _r/w rd input read ale_as ale input address latch enable cs cs input active-low chip select int int output active-hi g h interrupt rdy_dtack rdy output active-low read y ad [ 7:0 ] ad [ 7:0 ] i/o address/data bus
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 23 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p the re g ister bank architecture of the microprocessor interface is shown in table 14. all addresses referred to in this section are g iven in hexadecimal and binar y notation, where hexadecimal is the left column and binar y is the ri g ht column under address. note: bits in re g isters 0xc00xff can have one of four confi g urations, dependin g upon the settin g of re g ister 0xbf ( see the re g ister architecture description section, pa g e 57pa g e 59 ) . table 14. device re g ister ma p address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control, alarm, and mask bit registers 00 00000000 test_cnt b1errins b2errins b3errins latch_cnt blueclksel bipblkcnt 0 01 00000001 rei_en auto_lrdi txpaisins djactl 0 sts1scr sts1dscr sts1lb 02 00000010 rxserial txserial rxparity txparity rxsts1edge txsts1edge rxds1edge txds1edge 03 00000011 traceer rxparer 0 h4lomf sts1pais sts1lop sts1lof sts1oof 04 00000100 traceermsk rxparermsk 0 h4lomfmsk sts1paismsk sts1lopmsk sts1lofmsk sts1oofmsk 05 00000101 esofcom vtsizecom vtlopcom vtrfirdicom vtaiscom vtlabcom aisloccom sts1los 06 00000110 esofmsk vtsizemsk vtlopmsk vtrfirdimsk vtaismsk vtlabmsk aislocmsk sts1losmsk 07 00000111 0 0 0 0000ds1_e1n 08 00001000 latch_tp rcv_frame rcv_pat-1 rcv_pat-0 error_ins xmt_frame xmt_pat-1 xmt_pat-0 09 00001001 tp_ds1e1n tp_invert tpdropside tpdrop-4 tpdrop-3 tpdrop-2 tpdrop-1 tpdrop-0 0a 00001010 tpoos tperr-6 tperr-5 tperr-4 tperr-3 tperr-2 tperr-1 tperr-0 0b 00001011 f2-7 f2-6 f2-5 f2-4 f2-3 f2-2 f2-1 f2-0 0c 00001100 c2-7 c2-6 c2-5 c2-4 c2-3 c2-2 c2-1 c2-0 0d 00001101 g1-5 g1-6 g1-7 g1-8 0 k2-6 k2-7 k2-8 0e 00001110 c2#det-3 c2#det-2 c2#det-1 c2#det-0 f2#det-3 f2#det-2 f2#det-1 f2#det-0 0f 00001111 g1#det-3 g1#det-2 g1#det-1 g1#det-0 k2#det-3 k2#det-2 k2#det-1 k2#det-0 10 00010000 f2ins-7 f2ins-6 f2ins-5 f2ins-4 f2ins-3 f2ins-2 f2ins-1 f2ins-0 11 00010001 g1ins-5 g1ins-6 g1ins-7 g1ins-8 0 k2ins-6 k2ins-7 k2ins-8 12 00010010 0 0 rbusmode rbuspos-1 rbuspos-0 tbusmode tbuspos-1 tbuspos-0 13 00010011 0 0 0 0 s1ins-3 s1ins-2 s1ins-1 s1ins-0 14 00010100 s1#det-3 s1#det-2 s1#det-1 s1#det-0 s1-3 s1-2 s1-1 s1-0 15 00010101 devid-7 devid-6 devid-5 devid-4 devid-3 devid-2 devid-1 devid-0 16 00010110 0 0 0 0 devver-3 devver-2 devver-1 devver-0
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 24 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 insertion selection registers 17 00010111 ds1/e1ais1 ds1/e1loc1 ds1/e1lb1 ds1/e1ins4_1 ds1/e1ins3_1 ds1/e1ins2_1 ds1/e1ins1_1 ds1/e1ins0_1 18 00011000 ds1/e1ais2 ds1/e1loc2 ds1/e1lb2 ds1/e1ins4_2 ds1/e1ins3_2 ds1/e1ins2_2 ds1/e1ins1_2 ds1/e1ins0_2 19 00011001 ds1/e1ais3 ds1/e1loc3 ds1/e1lb3 ds1/e1ins4_3 ds1/e1ins3_3 ds1/e1ins2_3 ds1/e1ins1_3 ds1/e1ins0_3 1a 00011010 ds1/e1ais4 ds1/e1loc4 ds1/e1lb4 ds1/e1ins4_4 ds1/e1ins3_4 ds1/e1ins2_4 ds1/e1ins1_4 ds1/e1ins0_4 1b 00011011 ds1/e1ais5 ds1/e1loc5 ds1/e1lb5 ds1/e1ins4_5 ds1/e1ins3_5 ds1/e1ins2_5 ds1/e1ins1_5 ds1/e1ins0_5 1c 00011100 ds1/e1ais6 ds1/e1loc6 ds1/e1lb6 ds1/e1ins4_6 ds1/e1ins3_6 ds1/e1ins2_6 ds1/e1ins1_6 ds1/e1ins0_6 1d 00011101 ds1/e1ais7 ds1/e1loc7 ds1/e1lb7 ds1/e1ins4_7 ds1/e1ins3_7 ds1/e1ins2_7 ds1/e1ins1_7 ds1/e1ins0_7 1e 00011110 ds1/e1ais8 ds1/e1loc8 ds1/e1lb8 ds1/e1ins4_8 ds1/e1ins3_8 ds1/e1ins2_8 ds1/e1ins1_8 ds1/e1ins0_8 1f 00011111 ds1/e1ais9 ds1/e1loc9 ds1/e1lb9 ds1/e1ins4_9 ds1/e1ins3_9 ds1/e1ins2_9 ds1/e1ins1_9 ds1/e1ins0_9 20 00100000 ds1/e1ais10 ds1/e1loc10 ds1/e1lb10 ds1/e1ins4_10 ds1/e1ins3_10 ds1/e1ins2_10 ds1/e1ins1_10 ds1/e1ins0_10 21 00100001 ds1/e1ais11 ds1/e1loc11 ds1/e1lb11 ds1/e1ins4_11 ds1/e1ins3_11 ds1/e1ins2_11 ds1/e1ins1_11 ds1/e1ins0_11 22 00100010 ds1/e1ais12 ds1/e1loc12 ds1/e1lb12 ds1/e1ins4_12 ds1/e1ins3_12 ds1/e1ins2_12 ds1/e1ins1_12 ds1/e1ins0_12 23 00100011 ds1/e1ais13 ds1/e1loc13 ds1/e1lb13 ds1/e1ins4_13 ds1/e1ins3_13 ds1/e1ins2_13 ds1/e1ins1_13 ds1/e1ins0_13 24 00100100 ds1/e1ais14 ds1/e1loc14 ds1/e1lb14 ds1/e1ins4_14 ds1/e1ins3_14 ds1/e1ins2_14 ds1/e1ins1_14 ds1/e1ins0_14 25 00100101 ds1/e1ais15 ds1/e1loc15 ds1/e1lb15 ds1/e1ins4_15 ds1/e1ins3_15 ds1/e1ins2_15 ds1/e1ins1_15 ds1/e1ins0_15 26 00100110 ds1/e1ais16 ds1/e1loc16 ds1/e1lb16 ds1/e1ins4_16 ds1/e1ins3_16 ds1/e1ins2_16 ds1/e1ins1_16 ds1/e1ins0_16 27 00100111 ds1/e1ais17 ds1/e1loc17 ds1/e1lb17 ds1/e1ins4_17 ds1/e1ins3_17 ds1/e1ins2_17 ds1/e1ins1_17 ds1/e1ins0_17 28 00101000 ds1/e1ais18 ds1/e1loc18 ds1/e1lb18 ds1/e1ins4_18 ds1/e1ins3_18 ds1/e1ins2_18 ds1/e1ins1_18 ds1/e1ins0_18 29 00101001 ds1/e1ais19 ds1/e1loc19 ds1/e1lb19 ds1/e1ins4_19 ds1/e1ins3_19 ds1/e1ins2_19 ds1/e1ins1_19 ds1/e1ins0_19 2a 00101010 ds1/e1ais20 ds1/e1loc20 ds1/e1lb20 ds1/e1ins4_20 ds1/e1ins3_20 ds1/e1ins2_20 ds1/e1ins1_20 ds1/e1ins0_20 2b 00101011 ds1/e1ais21 ds1/e1loc21 ds1/e1lb21 ds1/e1ins4_21 ds1/e1ins3_21 ds1/e1ins2_21 ds1/e1ins1_21 ds1/e1ins0_21 2c 00101100 ds1ais22 ds1loc22 ds1lb22 ds1ins4_22 ds1ins3_22 ds1ins2_22 ds1ins1_22 ds1ins0_22 2d 00101101 ds1ais23 ds1loc23 ds1lb23 ds1ins4_23 ds1ins3_23 ds1ins2_23 ds1ins1_23 ds1ins0_23 2e 00101110 ds1ais24 ds1loc24 ds1lb24 ds1ins4_24 ds1ins3_24 ds1ins2_24 ds1ins1_24 ds1ins0_24 2f 00101111 ds1ais25 ds1loc25 ds1lb25 ds1ins4_25 ds1ins3_25 ds1ins2_25 ds1ins1_25 ds1ins0_25 30 00110000 ds1ais26 ds1loc26 ds1lb26 ds1ins4_26 ds1ins3_26 ds1ins2_26 ds1ins1_26 ds1ins0_26 31 00110001 ds1ais27 ds1loc27 ds1lb27 ds1ins4_27 ds1ins3_27 ds1ins2_27 ds1ins1_27 ds1ins0_27 32 00110010 ds1ais28 ds1loc28 ds1lb28 ds1ins4_28 ds1ins3_28 ds1ins2_28 ds1ins1_28 ds1ins0_28
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 25 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt drop selection registers 33 00110011 0 rxesof1 txesof1 vtdrop4_1 vtdrop3_1 vtdrop2_1 vtdrop1_1 vtdrop0_1 34 00110100 0 rxesof2 txesof2 vtdrop4_2 vtdrop3_2 vtdrop2_2 vtdrop1_2 vtdrop0_2 35 00110101 0 rxesof3 txesof3 vtdrop4_3 vtdrop3_3 vtdrop2_3 vtdrop1_3 vtdrop0_3 36 00110110 0 rxesof4 txesof4 vtdrop4_4 vtdrop3_4 vtdrop2_4 vtdrop1_4 vtdrop0_4 37 00110111 0 rxesof5 txesof5 vtdrop4_5 vtdrop3_5 vtdrop2_5 vtdrop1_5 vtdrop0_5 38 00111000 0 rxesof6 txesof6 vtdrop4_6 vtdrop3_6 vtdrop2_6 vtdrop1_6 vtdrop0_6 39 00111001 0 rxesof7 txesof7 vtdrop4_7 vtdrop3_7 vtdrop2_7 vtdrop1_7 vtdrop0_7 3a 00111010 0 rxesof8 txesof8 vtdrop4_8 vtdrop3_8 vtdrop2_8 vtdrop1_8 vtdrop0_8 3b 00111011 0 rxesof9 txesof9 vtdrop4_9 vtdrop3_9 vtdrop2_9 vtdrop1_9 vtdrop0_9 3c 00111100 0 rxesof10 txesof10 vtdrop4_10 vtdrop3_10 vtdrop2_10 vtdrop1_10 vtdrop0_10 3d 00111101 0 rxesof11 txesof11 vtdrop4_11 vtdrop3_11 vtdrop2_11 vtdrop1_11 vtdrop0_11 3e 00111110 0 rxesof12 txesof12 vtdrop4_12 vtdrop3_12 vtdrop2_12 vtdrop1_12 vtdrop0_12 3f 00111111 0 rxesof13 txesof13 vtdrop4_13 vtdrop3_13 vtdrop2_13 vtdrop1_13 vtdrop0_13 40 01000000 0 rxesof14 txesof14 vtdrop4_14 vtdrop3_14 vtdrop2_14 vtdrop1_14 vtdrop0_14 41 01000001 0 rxesof15 txesof15 vtdrop4_15 vtdrop3_15 vtdrop2_15 vtdrop1_15 vtdrop0_15 42 01000010 0 rxesof16 txesof16 vtdrop4_16 vtdrop3_16 vtdrop2_16 vtdrop1_16 vtdrop0_16 43 01000011 0 rxesof17 txesof17 vtdrop4_17 vtdrop3_17 vtdrop2_17 vtdrop1_17 vtdrop0_17 44 01000100 0 rxesof18 txesof18 vtdrop4_18 vtdrop3_18 vtdrop2_18 vtdrop1_18 vtdrop0_18 45 01000101 0 rxesof19 txesof19 vtdrop4_19 vtdrop3_19 vtdrop2_19 vtdrop1_19 vtdrop0_19 46 01000110 0 rxesof20 txesof20 vtdrop4_20 vtdrop3_20 vtdrop2_20 vtdrop1_20 vtdrop0_20 47 01000111 0 rxesof21 txesof21 vtdrop4_21 vtdrop3_21 vtdrop2_21 vtdrop1_21 vtdrop0_21 48 01001000 0 rxesof22 txesof22 vtdrop4_22 vtdrop3_22 vtdrop2_22 vtdrop1_22 vtdrop0_22 49 01001001 0 rxesof23 txesof23 vtdrop4_23 vtdrop3_23 vtdrop2_23 vtdrop1_23 vtdrop0_23 4a 01001010 0 rxesof24 txesof24 vtdrop4_24 vtdrop3_24 vtdrop2_24 vtdrop1_24 vtdrop0_24 4b 01001011 0 rxesof25 txesof25 vtdrop4_25 vtdrop3_25 vtdrop2_25 vtdrop1_25 vtdrop0_25 4c 01001100 0 rxesof26 txesof26 vtdrop4_26 vtdrop3_26 vtdrop2_26 vtdrop1_26 vtdrop0_26 4d 01001101 0 rxesof27 txesof27 vtdrop4_27 vtdrop3_27 vtdrop2_27 vtdrop1_27 vtdrop0_27 4e 01001110 0 rxesof28 txesof28 vtdrop4_28 vtdrop3_28 vtdrop2_28 vtdrop1_28 vtdrop0_28
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 26 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx vt overhead insertion control registers 4f 01001111 bip2erins1 vtrfirdien1 vtrfiins1 vtrdiins1 vtaisins1 vtlabins2_1 vtlabins1_1 vtlabins0_1 50 01010000 bip2erins2 vtrfirdien2 vtrfiins2 vtrdiins2 vtaisins2 vtlabins2_2 vtlabins1_2 vtlabins0_2 51 01010001 bip2erins3 vtrfirdien3 vtrfiins3 vtrdiins3 vtaisins3 vtlabins2_3 vtlabins1_3 vtlabins0_3 52 01010010 bip2erins4 vtrfirdien4 vtrfiins4 vtrdiins4 vtaisins4 vtlabins2_4 vtlabins1_4 vtlabins0_4 53 01010011 bip2erins5 vtrfirdien5 vtrfiins5 vtrdiins5 vtaisins5 vtlabins2_5 vtlabins1_5 vtlabins0_5 54 01010100 bip2erins6 vtrfirdien6 vtrfiins6 vtrdiins6 vtaisins6 vtlabins2_6 vtlabins1_6 vtlabins0_6 55 01010101 bip2erins7 vtrfirdien7 vtrfiins7 vtrdiins7 vtaisins7 vtlabins2_7 vtlabins1_7 vtlabins0_7 56 01010110 bip2erins8 vtrfirdien8 vtrfiins8 vtrdiins8 vtaisins8 vtlabins2_8 vtlabins1_8 vtlabins0_8 57 01010111 bip2erins9 vtrfirdien9 vtrfiins9 vtrdiins9 vtaisins9 vtlabins2_9 vtlabins1_9 vtlabins0_9 58 01011000 bip2erins10 vtrfirdien10 vtrfiins10 vtrdiins10 vtaisins10 vtlabins2_10 vtlabins1_10 vtlabins0_10 59 01011001 bip2erins11 vtrfirdien11 vtrfiins11 vtrdiins11 vtaisins11 vtlabins2_11 vtlabins1_11 vtlabins0_11 5a 01011010 bip2erins12 vtrfirdien12 vtrfiins12 vtrdiins12 vtaisins12 vtlabins2_12 vtlabins1_12 vtlabins0_12 5b 01011011 bip2erins13 vtrfirdien13 vtrfiins13 vtrdiins13 vtaisins13 vtlabins2_13 vtlabins1_13 vtlabins0_13 5c 01011100 bip2erins14 vtrfirdien14 vtrfiins14 vtrdiins14 vtaisins14 vtlabins2_14 vtlabins1_14 vtlabins0_14 5d 01011101 bip2erins15 vtrfirdien15 vtrfiins15 vtrdiins15 vtaisins15 vtlabins2_15 vtlabins1_15 vtlabins0_15 5e 01011110 bip2erins16 vtrfirdien16 vtrfiins16 vtrdiins16 vtaisins16 vtlabins2_16 vtlabins1_16 vtlabins0_16 5f 01011111 bip2erins17 vtrfirdien17 vtrfiins17 vtrdiins17 vtaisins17 vtlabins2_17 vtlabins1_17 vtlabins0_17 60 01100000 bip2erins18 vtrfirdien18 vtrfiins18 vtrdiins18 vtaisins18 vtlabins2_18 vtlabins1_18 vtlabins0_18 61 01100001 bip2erins19 vtrfirdien19 vtrfiins19 vtrdiins19 vtaisins19 vtlabins2_19 vtlabins1_19 vtlabins0_19 62 01100010 bip2erins20 vtrfirdien20 vtrfiins20 vtrdiins20 vtaisins20 vtlabins2_20 vtlabins1_20 vtlabins0_20 63 01100011 bip2erins21 vtrfirdien21 vtrfiins21 vtrdiins21 vtaisins21 vtlabins2_21 vtlabins1_21 vtlabins0_21 64 01100100 bip2erins22 vtrfirdien22 vtrfiins22 vtrdiins22 vtaisins22 vtlabins2_22 vtlabins1_22 vtlabins0_22 65 01100101 bip2erins23 vtrfirdien23 vtrfiins23 vtrdiins23 vtaisins23 vtlabins2_23 vtlabins1_23 vtlabins0_23 66 01100110 bip2erins24 vtrfirdien24 vtrfiins24 vtrdiins24 vtaisins24 vtlabins2_24 vtlabins1_24 vtlabins0_24 67 01100111 bip2erins25 vtrfirdien25 vtrfiins25 vtrdiins25 vtaisins25 vtlabins2_25 vtlabins1_25 vtlabins0_25 68 01101000 bip2erins26 vtrfirdien26 vtrfiins26 vtrdiins26 vtaisins26 vtlabins2_26 vtlabins1_26 vtlabins0_26 69 01101001 bip2erins27 vtrfirdien27 vtrfiins27 vtrdiins27 vtaisins27 vtlabins2_27 vtlabins1_27 vtlabins0_27 6a 01101010 bip2erins28 vtrfirdien28 vtrfiins28 vtrdiins28 vtaisins28 vtlabins2_28 vtlabins1_28 vtlabins0_28
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 27 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx vt drop monitoring registers 6b 01101011 vtsizeer1 vtlop1 vtrdi1_1 vtrdi0_1 vtais1 vtlab2_1 vtlab1_1 vtlab0_1 6c 01101100 vtsizeer2 vtlop2 vtrdi1_2 vtrdi0_2 vtais2 vtlab2_2 vtlab1_2 vtlab0_2 6d 01101101 vtsizeer3 vtlop3 vtrdi1_3 vtrdi0_3 vtais3 vtlab2_3 vtlab1_3 vtlab0_3 6e 01101110 vtsizeer4 vtlop4 vtrdi1_4 vtrdi0_4 vtais4 vtlab2_4 vtlab1_4 vtlab0_4 6f 01101111 vtsizeer5 vtlop5 vtrdi1_5 vtrdi0_5 vtais5 vtlab2_5 vtlab1_5 vtlab0_5 70 01110000 vtsizeer6 vtlop6 vtrdi1_6 vtrdi0_6 vtais6 vtlab2_6 vtlab1_6 vtlab0_6 71 01110001 vtsizeer7 vtlop7 vtrdi1_7 vtrdi0_7 vtais7 vtlab2_7 vtlab1_7 vtlab0_7 72 01110010 vtsizeer8 vtlop8 vtrdi1_8 vtrdi0_8 vtais8 vtlab2_8 vtlab1_8 vtlab0_8 73 01110011 vtsizeer9 vtlop9 vtrdi1_9 vtrdi0_9 vtais9 vtlab2_9 vtlab1_9 vtlab0_9 74 01110100 vtsizeer10 vtlop10 vtrdi1_10 vtrdi0_10 vtais10 vtlab2_10 vtlab1_10 vtlab0_10 75 01110101 vtsizeer11 vtlop11 vtrdi1_11 vtrdi0_11 vtais11 vtlab2_11 vtlab1_11 vtlab0_11 76 01110110 vtsizeer12 vtlop12 vtrdi1_12 vtrdi0_12 vtais12 vtlab2_12 vtlab1_12 vtlab0_12 77 01110111 vtsizeer13 vtlop13 vtrdi1_13 vtrdi0_13 vtais13 vtlab2_13 vtlab1_13 vtlab0_13 78 01111000 vtsizeer14 vtlop14 vtrdi1_14 vtrdi0_14 vtais14 vtlab2_14 vtlab1_14 vtlab0_14 79 01111001 vtsizeer15 vtlop15 vtrdi1_15 vtrdi0_15 vtais15 vtlab2_15 vtlab1_15 vtlab0_15 7a 01111010 vtsizeer16 vtlop16 vtrdi1_16 vtrdi0_16 vtais16 vtlab2_16 vtlab1_16 vtlab0_16 7b 01111011 vtsizeer17 vtlop17 vtrdi1_17 vtrdi0_17 vtais17 vtlab2_17 vtlab1_17 vtlab0_17 7c 01111100 vtsizeer18 vtlop18 vtrdi1_18 vtrdi0_18 vtais18 vtlab2_18 vtlab1_18 vtlab0_18 7d 01111101 vtsizeer19 vtlop19 vtrdi1_19 vtrdi0_19 vtais19 vtlab2_19 vtlab1_19 vtlab0_19 7e 01111110 vtsizeer20 vtlop20 vtrdi1_20 vtrdi0_20 vtais20 vtlab2_20 vtlab1_20 vtlab0_20 7f 01111111 vtsizeer21 vtlop21 vtrdi1_21 vtrdi0_21 vtais21 vtlab2_21 vtlab1_21 vtlab0_21 80 10000000 vtsizeer22 vtlop22 vtrdi1_22 vtrdi0_22 vtais22 vtlab2_22 vtlab1_22 vtlab0_22 81 10000001 vtsizeer23 vtlop23 vtrdi1_23 vtrdi0_23 vtais23 vtlab2_23 vtlab1_23 vtlab0_23 82 10000010 vtsizeer24 vtlop24 vtrdi1_24 vtrdi0_24 vtais24 vtlab2_24 vtlab1_24 vtlab0_24 83 10001000 vtsizeer25 vtlop25 vtrdi1_25 vtrdi0_25 vtais25 vtlab2_25 vtlab1_25 vtlab0_25 84 10000100 vtsizeer26 vtlop26 vtrdi1_26 vtrdi0_26 vtais26 vtlab2_26 vtlab1_26 vtlab0_26 85 10000101 vtsizeer27 vtlop27 vtrdi1_27 vtrdi0_27 vtais27 vtlab2_27 vtlab1_27 vtlab0_27 86 10000110 vtsizeer28 vtlop28 vtrdi1_28 vtrdi0_28 vtais28 vtlab2_28 vtlab1_28 vtlab0_28 reserved register 87 10000111 0 0 0 0 0 0 0 0 signal override control registers 88 10001000 tvtg-7 tvtg-6 tvtg-5 tvtg-4 tvtg-3 tvtg-2 tvtg-1 toverride 89 10001001 rvtg-7 rvtg-6 rvtg-5 rvtg-4 rvtg-3 rvtg-2 rvtg-1 roverride jitter attenuator control registers 8a 10001010 scalethr-7 scalethr-6 scalethr-5 scalethr-4 scalethr-3 scalethr-2 scalethr-1 scalethr-0 8b 10001011 djascale-15 djascale-14 djascale-13 djascale-12 djascale-11 djascale-10 djascale-9 djascale-8 8c 10001100 djascale-7 djascale-6 djascale-5 djascale-4 djascale-3 djascale-2 djascale-1 djascale-0 8d 10001101 djagthr-23 djagthr-22 djagthr-21 djagthr-20 djagthr-19 djagthr-18 djagthr-17 djagthr-16 8e 10001110 djagthr-15 djagthr-14 djagthr-13 djagthr-12 djagthr-11 djagthr-10 djagthr-9 djagthr-8 8f 10001111 djagthr-7 djagthr-6 djagthr-5 djagthr-4 djagthr-3 djagthr-2 djagthr-1 djagthr-0
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 28 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved register 90 10010000 00000000 sts-1 los detect/test pattern edge control register 91 10010001 losdet-7 losdet-6 losdet-5 losdet-4 losdet-3 losdet-2 losdet-1/ tp_edge-1 losdet-0/ tp_edge-0 reserved registers 92 10010010 reserved reserved reserved reserved reserved reserved reserved reserved 93 10010011 reserved reserved reserved reserved reserved reserved reserved reserved 94 10010100 reserved reserved reserved reserved reserved reserved reserved reserved 95 10010101 reserved reserved reserved reserved reserved reserved reserved reserved 96 10010110 reserved reserved reserved reserved reserved reserved reserved reserved 97 10010111 reserved reserved reserved reserved reserved reserved reserved reserved 98 10011000 reserved reserved reserved reserved reserved reserved reserved reserved 99 10011001 reserved reserved reserved reserved reserved reserved reserved reserved 9a 10011010 reserved reserved reserved reserved reserved reserved reserved reserved 9b 10011011 reserved reserved reserved reserved reserved reserved reserved reserved 9c 10011100 reserved reserved reserved reserved reserved reserved reserved reserved 9d 10011101 reserved reserved reserved reserved reserved reserved reserved reserved 9e 10011110 reserved reserved reserved reserved reserved reserved reserved reserved 9f 10011111 reserved reserved reserved reserved reserved reserved reserved reserved a0 10100000 reserved reserved reserved reserved reserved reserved reserved reserved a1 10100001 reserved reserved reserved reserved reserved reserved reserved reserved a2 10100010 reserved reserved reserved reserved reserved reserved reserved reserved a3 10100011 reserved reserved reserved reserved reserved reserved reserved reserved a4 10100100 reserved reserved reserved reserved reserved reserved reserved reserved a5 10100101 reserved reserved reserved reserved reserved reserved reserved reserved a6 10100110 reserved reserved reserved reserved reserved reserved reserved reserved a7 10100111 reserved reserved reserved reserved reserved reserved reserved reserved a8 10101000 reserved reserved reserved reserved reserved reserved reserved reserved a9 10101001 reserved reserved reserved reserved reserved reserved reserved reserved aa 10101010 reserved reserved reserved reserved reserved reserved reserved reserved ab 10101011 reserved reserved reserved reserved reserved reserved reserved reserved ac 10101100 reserved reserved reserved reserved reserved reserved reserved reserved ad 10101101 reserved reserved reserved reserved reserved reserved reserved reserved ae 10101110 reserved reserved reserved reserved reserved reserved reserved reserved af 10101111 reserved reserved reserved reserved reserved reserved reserved reserved b0 10110000 reserved reserved reserved reserved reserved reserved reserved reserved b1 10110001 reserved reserved reserved reserved reserved reserved reserved reserved b2 10110010 reserved reserved reserved reserved reserved reserved reserved reserved b3 10110011 reserved reserved reserved reserved reserved reserved reserved reserved b4 10110100 reserved reserved reserved reserved reserved reserved reserved reserved
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 29 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved registers ( continued ) b5 10110101 reserved reserved reserved reserved reserved reserved reserved reserved b6 10110110 reserved reserved reserved reserved reserved reserved reserved reserved b7 10110111 reserved reserved reserved reserved reserved reserved reserved reserved b8 10111000 reserved reserved reserved reserved reserved reserved reserved reserved b9 10111001 reserved reserved reserved reserved reserved reserved reserved reserved ba 10111010 reserved reserved reserved reserved reserved reserved reserved reserved bb 10111011 reserved reserved reserved reserved reserved reserved reserved reserved bc 10111100 reserved reserved reserved reserved reserved reserved reserved reserved bd 10111101 reserved reserved reserved reserved reserved reserved reserved reserved be 10111110 reserved reserved reserved reserved reserved reserved reserved reserved block control register bf 10111111 0 0 0 0 tj1byte rj1byte rei_cnts bip_cnts block registers 0xc00xff: detected bip errors re g ister 0xbf settin g : bip_cnts = 1 c0 11000000 b1bipcnt-15 b1bipcnt-14 b1bipcnt-13 b1bipcnt-12 b1bipcnt-11 b1bipcnt-10 b1bipcnt-9 b1bipcnt-8 c1 11000001 b1bipcnt-7 b1bipcnt-6 b1bipcnt-5 b1bipcnt-4 b1bipcnt-3 b1bipcnt-2 b1bipcnt-1 b1bipcnt-0 c2 11000010 b2bipcnt-15 b2bipcnt-14 b2bipcnt-13 b2bipcnt-12 b2bipcnt-11 b2bipcnt-10 b2bipcnt-9 b2bipcnt-8 c3 11000011 b2bipcnt-7 b2bipcnt-6 b2bipcnt-5 b2bipcnt-4 b2bipcnt-3 b2bipcnt-2 b2bipcnt-1 b2bipcnt-0 c4 11000100 b3bipcnt-15 b3bipcnt-14 b3bipcnt-13 b3bipcnt-12 b3bipcnt-11 b3bipcnt-10 b3bipcnt-9 b3bipcnt-8 c5 11000101 b3bipcnt-7 b3bipcnt-6 b3bipcnt-5 b3bipcnt-4 b3bipcnt-3 b3bipcnt-2 b3bipcnt-1 b3bipcnt-0 c6 11000110 vt1ptr+3 vt1ptr+2 vt1ptr+1 vt1ptr+0 bip2cnt11_1 bip2cnt10_1 bip2cnt9_1 bip2cnt8_1 c7 11000111 bip2cnt7_1 bip2cnt6_1 bip2cnt5_1 bip2cnt4_1 bip2cnt3_1 bip2cnt2_1 bip2cnt1_1 bip2cnt0_1 c8 11001000 vt2ptr+3 vt2ptr+2 vt2ptr+1 vt2ptr+0 bip2cnt11_2 bip2cnt10_2 bip2cnt9_2 bip2cnt8_2 c9 11001001 bip2cnt7_2 bip2cnt6_2 bip2cnt5_2 bip2cnt4_2 bip2cnt3_2 bip2cnt2_2 bip2cnt1_2 bip2cnt0_2 ca 11001010 vt3ptr+3 vt3ptr+2 vt3ptr+1 vt3ptr+0 bip2cnt11_3 bip2cnt10_3 bip2cnt9_3 bip2cnt8_3 cb 11001011 bip2cnt7_3 bip2cnt6_3 bip2cnt5_3 bip2cnt4_3 bip2cnt3_3 bip2cnt2_3 bip2cnt1_3 bip2cnt0_3 cc 11001100 vt4ptr+3 vt4ptr+2 vt4ptr+1 vt4ptr+0 bip2cnt11_4 bip2cnt10_4 bip2cnt9_4 bip2cnt8_4 cd 11001101 bip2cnt7_4 bip2cnt6_4 bip2cnt5_4 bip2cnt4_4 bip2cnt3_4 bip2cnt2_4 bip2cnt1_4 bip2cnt0_4 ce 11001110 vt5ptr+3 vt5ptr+2 vt5ptr+1 vt5ptr+0 bip2cnt11_5 bip2cnt10_5 bip2cnt9_5 bip2cnt8_5 cf 11001111 bip2cnt7_5 bip2cnt6_5 bip2cnt5_5 bip2cnt4_5 bip2cnt3_5 bip2cnt2_5 bip2cnt1_5 bip2cnt0_5 d0 11010000 vt6ptr+3 vt6ptr+2 vt6ptr+1 vt6ptr+0 bip2cnt11_6 bip2cnt10_6 bip2cnt9_6 bip2cnt8_6 d1 11010001 bip2cnt7_6 bip2cnt6_6 bip2cnt5_6 bip2cnt4_6 bip2cnt3_6 bip2cnt2_6 bip2cnt1_6 bip2cnt0_6 d2 11010010 vt7ptr+3 vt7ptr+2 vt7ptr+1 vt7ptr+0 bip2cnt11_7 bip2cnt10_7 bip2cnt9_7 bip2cnt8_7 d3 11010011 bip2cnt7_7 bip2cnt6_7 bip2cnt5_7 bip2cnt4_7 bip2cnt3_7 bip2cnt2_7 bip2cnt1_7 bip2cnt0_7 d4 11010100 vt8ptr+3 vt8ptr+2 vt8ptr+1 vt8ptr+0 bip2cnt11_8 bip2cnt10_8 bip2cnt9_8 bip2cnt8_8 d5 11010101 bip2cnt7_8 bip2cnt6_8 bip2cnt5_8 bip2cnt4_8 bip2cnt3_8 bip2cnt2_8 bip2cnt1_8 bip2cnt0_8 d6 11010110 vt9ptr+3 vt9ptr+2 vt9ptr+1 vt9ptr+0 bip2cnt11_9 bip2cnt10_9 bip2cnt9_9 bip2cnt8_9 d7 11010111 bip2cnt7_9 bip2cnt6_9 bip2cnt5_9 bip2cnt4_9 bip2cnt3_9 bip2cnt2_9 bip2cnt1_9 bip2cnt0_9 d8 11011000 vt10ptr+3 vt10ptr+2 vt10ptr+1 vt10ptr+0 bip2cnt11_10 bip2cnt10_10 bip2cnt9_10 bip2cnt8_10 d9 11011001 bip2cnt7_10 bip2cnt6_10 bip2cnt5_10 bip2cnt4_10 bip2cnt3_10 bip2cnt2_10 bip2cnt1_10 bip2cnt0_10
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 30 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: detected bip errors ( continued ) da 11011010 vt11ptr+3 vt11ptr+2 vt11ptr+1 vt11ptr+0 bip2cnt11_11 bip2cnt10_11 bip2cnt9_11 bip2cnt8_11 db 11011011 bip2cnt7_11 bip2cnt6_11 bip2cnt5_11 bip2cnt4_11 bip2cnt3_11 bip2cnt2_11 bip2cnt1_11 bip2cnt0_11 dc 11011100 vt12ptr+3 vt12ptr+2 vt12ptr+1 vt12ptr+0 bip2cnt11_12 bip2cnt10_12 bip2cnt9_12 bip2cnt8_12 dd 11011101 bip2cnt7_12 bip2cnt6_12 bip2cnt5_12 bip2cnt4_12 bip2cnt3_12 bip2cnt2_12 bip2cnt1_12 bip2cnt0_12 de 11011110 vt13ptr+3 vt13ptr+2 vt13ptr+1 vt13ptr+0 bip2cnt11_13 bip2cnt10_13 bip2cnt9_13 bip2cnt8_13 df 11011111 bip2cnt7_13 bip2cnt6_13 bip2cnt5_13 bip2cnt4_13 bip2cnt3_13 bip2cnt2_13 bip2cnt1_13 bip2cnt0_13 e0 11100000 vt14ptr+3 vt14ptr+2 vt14ptr+1 vt14ptr+0 bip2cnt11_14 bip2cnt10_14 bip2cnt9_14 bip2cnt8_14 e1 11100001 bip2cnt7_14 bip2cnt6_14 bip2cnt5_14 bip2cnt4_14 bip2cnt3_14 bip2cnt2_14 bip2cnt1_14 bip2cnt0_14 e2 11100010 vt15ptr+3 vt15ptr+2 vt15ptr+1 vt15ptr+0 bip2cnt11_15 bip2cnt10_15 bip2cnt9_15 bip2cnt8_15 e3 11100011 bip2cnt7_15 bip2cnt6_15 bip2cnt5_15 bip2cnt4_15 bip2cnt3_15 bip2cnt2_15 bip2cnt1_15 bip2cnt0_15 e4 11100100 vt16ptr+3 vt16ptr+2 vt16ptr+1 vt16ptr+0 bip2cnt11_16 bip2cnt10_16 bip2cnt9_16 bip2cnt8_16 e5 11100101 bip2cnt7_16 bip2cnt6_16 bip2cnt5_16 bip2cnt4_16 bip2cnt3_16 bip2cnt2_16 bip2cnt1_16 bip2cnt0_16 e6 11100110 vt17ptr+3 vt17ptr+2 vt17ptr+1 vt17ptr+0 bip2cnt11_17 bip2cnt10_17 bip2cnt9_17 bip2cnt8_17 e7 11100111 bip2cnt7_17 bip2cnt6_17 bip2cnt5_17 bip2cnt4_17 bip2cnt3_17 bip2cnt2_17 bip2cnt1_17 bip2cnt0_17 e8 11101000 vt18ptr+3 vt18ptr+2 vt18ptr+1 vt18ptr+0 bip2cnt11_18 bip2cnt10_18 bip2cnt9_18 bip2cnt8_18 e9 11101001 bip2cnt7_18 bip2cnt6_18 bip2cnt5_18 bip2cnt4_18 bip2cnt3_18 bip2cnt2_18 bip2cnt1_18 bip2cnt0_18 ea 11101010 vt19ptr+3 vt19ptr+2 vt19ptr+1 vt19ptr+0 bip2cnt11_19 bip2cnt10_19 bip2cnt9_19 bip2cnt8_19 eb 11101011 bip2cnt7_19 bip2cnt6_19 bip2cnt5_19 bip2cnt4_19 bip2cnt3_19 bip2cnt2_19 bip2cnt1_19 bip2cnt0_19 ec 11101100 vt20ptr+3 vt20ptr+2 vt20ptr+1 vt20ptr+0 bip2cnt11_20 bip2cnt10_20 bip2cnt9_20 bip2cnt8_20 ed 11101101 bip2cnt7_20 bip2cnt6_20 bip2cnt5_20 bip2cnt4_20 bip2cnt3_20 bip2cnt2_20 bip2cnt1_20 bip2cnt0_20 ee 11101110 vt21ptr+3 vt21ptr+2 vt21ptr+1 vt21ptr+0 bip2cnt11_21 bip2cnt10_21 bip2cnt9_21 bip2cnt8_21 ef 11101111 bip2cnt7_21 bip2cnt6_21 bip2cnt5_21 bip2cnt4_21 bip2cnt3_21 bip2cnt2_21 bip2cnt1_21 bip2cnt0_21 f0 11110000 vt22ptr+3 vt22ptr+2 vt22ptr+1 vt22ptr+0 bip2cnt11_22 bip2cnt10_22 bip2cnt9_22 bip2cnt8_22 f1 11110001 bip2cnt7_22 bip2cnt6_22 bip2cnt5_22 bip2cnt4_22 bip2cnt3_22 bip2cnt2_22 bip2cnt1_22 bip2cnt0_22 f2 11110010 vt23ptr+3 vt23ptr+2 vt23ptr+1 vt23ptr+0 bip2cnt11_23 bip2cnt10_23 bip2cnt9_23 bip2cnt8_23 f3 11110011 bip2cnt7_23 bip2cnt6_23 bip2cnt5_23 bip2cnt4_23 bip2cnt3_23 bip2cnt2_23 bip2cnt1_23 bip2cnt0_23 f4 11110100 vt24ptr+3 vt24ptr+2 vt24ptr+1 vt24ptr+0 bip2cnt11_24 bip2cnt10_24 bip2cnt9_24 bip2cnt8_24 f5 11110101 bip2cnt7_24 bip2cnt6_24 bip2cnt5_24 bip2cnt4_24 bip2cnt3_24 bip2cnt2_24 bip2cnt1_24 bip2cnt0_24 f6 11110110 vt25ptr+3 vt25ptr+2 vt25ptr+1 vt25ptr+0 bip2cnt11_25 bip2cnt10_25 bip2cnt9_25 bip2cnt8_25 f7 11110111 bip2cnt7_25 bip2cnt6_25 bip2cnt5_25 bip2cnt4_25 bip2cnt3_25 bip2cnt2_25 bip2cnt1_25 bip2cnt0_25 f8 11111000 vt26ptr+3 vt26ptr+2 vt26ptr+1 vt26ptr+0 bip2cnt11_26 bip2cnt10_26 bip2cnt9_26 bip2cnt8_26 f9 11111001 bip2cnt7_26 bip2cnt6_26 bip2cnt5_26 bip2cnt4_26 bip2cnt3_26 bip2cnt2_26 bip2cnt1_26 bip2cnt0_26 fa 11111010 vt27ptr+3 vt27ptr+2 vt27ptr+1 vt27ptr+0 bip2cnt11_27 bip2cnt10_27 bip2cnt9_27 bip2cnt8_27 fb 11111011 bip2cnt7_27 bip2cnt6_27 bip2cnt5_27 bip2cnt4_27 bip2cnt3_27 bip2cnt2_27 bip2cnt1_27 bip2cnt0_27 fc 11111100 vt28ptr+3 vt28ptr+2 vt28ptr+1 vt28ptr+0 bip2cnt11_28 bip2cnt10_28 bip2cnt9_28 bip2cnt8_28 fd 11111101 bip2cnt7_28 bip2cnt6_28 bip2cnt5_28 bip2cnt4_28 bip2cnt3_28 bip2cnt2_28 bip2cnt1_28 bip2cnt0_28 received sonet/sdh pointer value registers re g ister 0xbf settin g : bip_cnts = 1 fe 11111110 sptr+7 sptr+6 sptr+5 sptr+4 sptr+3 sptr+2 sptr+1 sptr+0 ff 11111111 sptrC7 sptrC6 sptrC5 sptrC4 sptrC3 sptrC2 sptrC1 sptrC0
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 31 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: detected rei errors re g ister 0xbf settin g s: rei_cnts = 1, bip_cnts = 0 c0 11000000 0 0 0 00000 c1 11000001 0 0 0 00000 c2 11000010 b2rei-15 b2rei-14 b2rei-13 b2rei-12 b2rei-11 b2rei-10 b2rei-9 b2rei-8 c3 11000011 b2rei-7 b2rei-6 b2rei-5 b2rei-4 b2rei-3 b2rei-2 b2rei-1 b2rei-0 c4 11000100 b3rei-15 b3rei-14 b3rei-13 b3rei-12 b3rei-11 b3rei-10 b3rei-9 b3rei-8 c5 11000101 b3rei-7 b3rei-6 b3rei-5 b3rei-4 b3rei-3 b3rei-2 b3rei-1 b3rei-0 c6 11000110 vt1ptrC3 vt1ptrC2 vt1ptrC1 vt1ptrC0 0 vtrei10_1 vtrei9_1 vtrei8_1 c7 11000111 vtrei7_1 vtrei6_1 vtrei5_1 vtrei4_1 vtrei3_1 vtrei2_1 vtrei1_1 vtrei0_1 c8 11001000 vt2ptrC3 vt2ptrC2 vt2ptrC1 vt2ptrC0 0 vtrei10_2 vtrei9_2 vtrei8_2 c9 11001001 vtrei7_2 vtrei6_2 vtrei5_2 vtrei4_2 vtrei3_2 vtrei2_2 vtrei1_2 vtrei0_2 ca 11001010 vt3ptrC3 vt3ptrC2 vt3ptrC1 vt3ptrC0 0 vtrei10_3 vtrei9_3 vtrei8_3 cb 11001011 vtrei7_3 vtrei6_3 vtrei5_3 vtrei4_3 vtrei3_3 vtrei2_3 vtrei1_3 vtrei0_3 cc 11001100 vt4ptrC3 vt4ptrC2 vt4ptrC1 vt4ptrC0 0 vtrei10_4 vtrei9_4 vtrei8_4 cd 11001101 vtrei7_4 vtrei6_4 vtrei5_4 vtrei4_4 vtrei3_4 vtrei2_4 vtrei1_4 vtrei0_4 ce 11001110 vt5ptrC3 vt5ptrC2 vt5ptrC1 vt5ptrC0 0 vtrei10_5 vtrei9_5 vtrei8_5 cf 11001111 vtrei7_5 vtrei6_5 vtrei5_5 vtrei4_5 vtrei3_5 vtrei2_5 vtrei1_5 vtrei0_5 d0 11010000 vt6ptrC3 vt6ptrC2 vt6ptrC1 vt6ptrC0 0 vtrei10_6 vtrei9_6 vtrei8_6 d1 11010001 vtrei7_6 vtrei6_6 vtrei5_6 vtrei4_6 vtrei3_6 vtrei2_6 vtrei1_6 vtrei0_6 d2 11010010 vt7ptrC3 vt7ptrC2 vt7ptrC1 vt7ptrC0 0 vtrei10_7 vtrei9_7 vtrei8_7 d3 11010011 vtrei7_7 vtrei6_7 vtrei5_7 vtrei4_7 vtrei3_7 vtrei2_7 vtrei1_7 vtrei0_7 d4 11010100 vt8ptrC3 vt8ptrC2 vt8ptrC1 vt8ptrC0 0 vtrei10_8 vtrei9_8 vtrei8_8 d5 11010101 vtrei7_8 vtrei6_8 vtrei5_8 vtrei4_8 vtrei3_8 vtrei2_8 vtrei1_8 vtrei0_8 d6 11010110 vt9ptrC3 vt9ptrC2 vt9ptrC1 vt9ptrC0 0 vtrei10_9 vtrei9_9 vtrei8_9 d7 11010111 vtrei7_9 vtrei6_9 vtrei5_9 vtrei4_9 vtrei3_9 vtrei2_9 vtrei1_9 vtrei0_9 d8 11011000 vt10ptrC3 vt10ptrC2 vt10ptrC1 vt10ptrC0 0 vtrei10_10 vtrei9_10 vtrei8_10 d9 11011001 vtrei7_10 vtrei6_10 vtrei5_10 vtrei4_10 vtrei3_10 vtrei2_10 vtrei1_10 vtrei0_10 da 11011010 vt11ptrC3 vt11ptrC2 vt11ptrC1 vt11ptrC0 0 vtrei10_11 vtrei9_11 vtrei8_11 db 11011011 vtrei7_11 vtrei6_11 vtrei5_11 vtrei4_11 vtrei3_11 vtrei2_11 vtrei1_11 vtrei0_11 dc 11011100 vt12ptrC3 vt12ptrC2 vt12ptrC1 vt12ptrC0 0 vtrei10_12 vtrei9_12 vtrei8_12 dd 11011101 vtrei7_12 vtrei6_12 vtrei5_12 vtrei4_12 vtrei3_12 vtrei2_12 vtrei1_12 vtrei0_12 de 11011110 vt13ptrC3 vt13ptrC2 vt13ptrC1 vt13ptrC0 0 vtrei10_13 vtrei9_13 vtrei8_13 df 11011111 vtrei7_13 vtrei6_13 vtrei5_13 vtrei4_13 vtrei3_13 vtrei2_13 vtrei1_13 vtrei0_13 e0 11100000 vt14ptrC3 vt14ptrC2 vt14ptrC1 vt14ptrC0 0 vtrei10_14 vtrei9_14 vtrei8_14 e1 11100001 vtrei7_14 vtrei6_14 vtrei5_14 vtrei4_14 vtrei3_14 vtrei2_14 vtrei1_14 vtrei0_14 e2 11100010 vt15ptrC3 vt15ptrC2 vt15ptrC1 vt15ptrC0 0 vtrei10_15 vtrei9_15 vtrei8_15 e3 11100011 vtrei7_15 vtrei6_15 vtrei5_15 vtrei4_15 vtrei3_15 vtrei2_15 vtrei1_15 vtrei0_15 e4 11100100 vt16ptrC3 vt16ptrC2 vt16ptrC1 vt16ptrC0 0 vtrei10_16 vtrei9_16 vtrei8_16 e5 11100101 vtrei7_16 vtrei6_16 vtrei5_16 vtrei4_16 vtrei3_16 vtrei2_16 vtrei1_16 vtrei0_16 e6 11100110 vt17ptrC3 vt17ptrC2 vt17ptrC1 vt17ptrC0 0 vtrei10_17 vtrei9_17 vtrei8_17 e7 11100111 vtrei7_17 vtrei6_17 vtrei5_17 vtrei4_17 vtrei3_17 vtrei2_17 vtrei1_17 vtrei0_17 e8 11101000 vt18ptrC3 vt18ptrC2 vt18ptrC1 vt18ptrC0 0 vtrei10_18 vtrei9_18 vtrei8_18 e9 11101001 vtrei7_18 vtrei6_18 vtrei5_18 vtrei4_18 vtrei3_18 vtrei2_18 vtrei1_18 vtrei0_18 ea 11101010 vt19ptrC3 vt19ptrC2 vt19ptrC1 vt19ptrC0 0 vtrei10_19 vtrei9_19 vtrei8_19
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 32 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: detected rei errors ( continued ) eb 11101011 vtrei7_19 vtrei6_19 vtrei5_19 vtrei4_19 vtrei3_19 vtrei2_19 vtrei1_19 vtrei0_19 ec 11101100 vt20ptrC3 vt20ptrC2 vt20ptrC1 vt20ptrC0 0 vtrei10_20 vtrei9_20 vtrei8_20 ed 11101101 vtrei7_20 vtrei6_20 vtrei5_20 vtrei4_20 vtrei3_20 vtrei2_20 vtrei1_20 vtrei0_20 ee 11101110 vt21ptrC3 vt21ptrC2 vt21ptrC1 vt21ptrC0 0 vtrei10_21 vtrei9_21 vtrei8_21 ef 11101111 vtrei7_21 vtrei6_21 vtrei5_21 vtrei4_21 vtrei3_21 vtrei2_21 vtrei1_21 vtrei0_21 f0 11110000 vt22ptrC3 vt22ptrC2 vt22ptrC1 vt22ptrC0 0 vtrei10_22 vtrei9_22 vtrei8_22 f1 11110001 vtrei7_22 vtrei6_22 vtrei5_22 vtrei4_22 vtrei3_22 vtrei2_22 vtrei1_22 vtrei0_22 f2 11110010 vt23ptrC3 vt23ptrC2 vt23ptrC1 vt23ptrC0 0 vtrei10_23 vtrei9_23 vtrei8_23 f3 11110011 vtrei7_23 vtrei6_23 vtrei5_23 vtrei4_23 vtrei3_23 vtrei2_23 vtrei1_23 vtrei0_23 f4 11110100 vt24ptrC3 vt24ptrC2 vt24ptrC1 vt24ptrC0 0 vtrei10_24 vtrei9_24 vtrei8_24 f5 11110101 vtrei7_24 vtrei6_24 vtrei5_24 vtrei4_24 vtrei3_24 vtrei2_24 vtrei1_24 vtrei0_24 f6 11110110 vt25ptrC3 vt25ptrC2 vt25ptrC1 vt25ptrC0 0 vtrei10_25 vtrei9_25 vtrei8_25 f7 11110111 vtrei7_25 vtrei6_25 vtrei5_25 vtrei4_25 vtrei3_25 vtrei2_25 vtrei1_25 vtrei0_25 f8 11111000 vt26ptrC3 vt26ptrC2 vt26ptrC1 vt26ptrC0 0 vtrei10_26 vtrei9_26 vtrei8_26 f9 11111001 vtrei7_26 vtrei6_26 vtrei5_26 vtrei4_26 vtrei3_26 vtrei2_26 vtrei1_26 vtrei0_26 fa 11111010 vt27ptrC3 vt27ptrC2 vt27ptrC1 vt27ptrC0 0 vtrei10_27 vtrei9_27 vtrei8_27 fb 11111011 vtrei7_27 vtrei6_27 vtrei5_27 vtrei4_27 vtrei3_27 vtrei2_27 vtrei1_27 vtrei0_27 fc 11111100 vt28ptrC3 vt28ptrC2 vt28ptrC1 vt28ptrC0 0 vtrei10_28 vtrei9_28 vtrei8_28 fd 11111101 vtrei7_28 vtrei6_28 vtrei5_28 vtrei4_28 vtrei3_28 vtrei2_28 vtrei1_28 vtrei0_28 fe 11111110 0 0 0 00000 ff 11111111 0 0 0 00000
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 33 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: receive j1 path trace bytes re g ister 0xbf settin g s: rj1byte = 1, bip_cnts = 0, rei_cnts = 0 c0 11000000 rj1byte7_64 rj1byte6_64 rj1byte5_64 rj1byte4_64 rj1byte3_64 rj1byte2_64 rj1byte1_64 rj1byte0_64 c1 11000001 rj1byte7_63 rj1byte6_63 rj1byte5_63 rj1byte4_63 rj1byte3_63 rj1byte2_63 rj1byte1_63 rj1byte0_63 c2 11000010 rj1byte7_62 rj1byte6_62 rj1byte5_62 rj1byte4_62 rj1byte3_62 rj1byte2_62 rj1byte1_62 rj1byte0_62 c3 11000011 rj1byte7_61 rj1byte6_61 rj1byte5_61 rj1byte4_61 rj1byte3_61 rj1byte2_61 rj1byte1_61 rj1byte0_61 c4 11000100 rj1byte7_60 rj1byte6_60 rj1byte5_60 rj1byte4_60 rj1byte3_60 rj1byte2_60 rj1byte1_60 rj1byte0_60 c5 11000101 rj1byte7_59 rj1byte6_59 rj1byte5_59 rj1byte4_59 rj1byte3_59 rj1byte2_59 rj1byte1_59 rj1byte0_59 c6 11000110 rj1byte7_58 rj1byte6_58 rj1byte5_58 rj1byte4_58 rj1byte3_58 rj1byte2_58 rj1byte1_58 rj1byte0_58 c7 11000111 rj1byte7_57 rj1byte6_57 rj1byte5_57 rj1byte4_57 rj1byte3_57 rj1byte2_57 rj1byte1_57 rj1byte0_57 c8 11001000 rj1byte7_56 rj1byte6_56 rj1byte5_56 rj1byte4_56 rj1byte3_56 rj1byte2_56 rj1byte1_56 rj1byte0_56 c9 11001001 rj1byte7_55 rj1byte6_55 rj1byte5_55 rj1byte4_55 rj1byte3_55 rj1byte2_55 rj1byte1_55 rj1byte0_55 ca 11001010 rj1byte7_54 rj1byte6_54 rj1byte5_54 rj1byte4_54 rj1byte3_54 rj1byte2_54 rj1byte1_54 rj1byte0_54 cb 11001011 rj1byte7_53 rj1byte6_53 rj1byte5_53 rj1byte4_53 rj1byte3_53 rj1byte2_53 rj1byte1_53 rj1byte0_53 cc 11001100 rj1byte7_52 rj1byte6_52 rj1byte5_52 rj1byte4_52 rj1byte3_52 rj1byte2_52 rj1byte1_52 rj1byte0_52 cd 11001101 rj1byte7_51 rj1byte6_51 rj1byte5_51 rj1byte4_51 rj1byte3_51 rj1byte2_51 rj1byte1_51 rj1byte0_51 ce 11001110 rj1byte7_50 rj1byte6_50 rj1byte5_50 rj1byte4_50 rj1byte3_50 rj1byte2_50 rj1byte1_50 rj1byte0_50 cf 11001111 rj1byte7_49 rj1byte6_49 rj1byte5_49 rj1byte4_49 rj1byte3_49 rj1byte2_49 rj1byte1_49 rj1byte0_49 d0 11010000 rj1byte7_48 rj1byte6_48 rj1byte5_48 rj1byte4_48 rj1byte3_48 rj1byte2_48 rj1byte1_48 rj1byte0_48 d1 11010001 rj1byte7_47 rj1byte6_47 rj1byte5_47 rj1byte4_47 rj1byte3_47 rj1byte2_47 rj1byte1_47 rj1byte0_47 d2 11010010 rj1byte7_46 rj1byte6_46 rj1byte5_46 rj1byte4_46 rj1byte3_46 rj1byte2_46 rj1byte1_46 rj1byte0_46 d3 11010011 rj1byte7_45 rj1byte6_45 rj1byte5_45 rj1byte4_45 rj1byte3_45 rj1byte2_45 rj1byte1_45 rj1byte0_45 d4 11010100 rj1byte7_44 rj1byte6_44 rj1byte5_44 rj1byte4_44 rj1byte3_44 rj1byte2_44 rj1byte1_44 rj1byte0_44 d5 11010101 rj1byte7_43 rj1byte6_43 rj1byte5_43 rj1byte4_43 rj1byte3_43 rj1byte2_43 rj1byte1_43 rj1byte0_43 d6 11010110 rj1byte7_42 rj1byte6_42 rj1byte5_42 rj1byte4_42 rj1byte3_42 rj1byte2_42 rj1byte1_42 rj1byte0_42 d7 11010111 rj1byte7_41 rj1byte6_41 rj1byte5_41 rj1byte4_41 rj1byte3_41 rj1byte2_41 rj1byte1_41 rj1byte0_41 d8 11011000 rj1byte7_40 rj1byte6_40 rj1byte5_40 rj1byte4_40 rj1byte3_40 rj1byte2_40 rj1byte1_40 rj1byte0_40 d9 11011001 rj1byte7_39 rj1byte6_39 rj1byte5_39 rj1byte4_39 rj1byte3_39 rj1byte2_39 rj1byte1_39 rj1byte0_39 da 11011010 rj1byte7_38 rj1byte6_38 rj1byte5_38 rj1byte4_38 rj1byte3_38 rj1byte2_38 rj1byte1_38 rj1byte0_38 db 11011011 rj1byte7_37 rj1byte6_37 rj1byte5_37 rj1byte4_37 rj1byte3_37 rj1byte2_37 rj1byte1_37 rj1byte0_37 dc 11011100 rj1byte7_36 rj1byte6_36 rj1byte5_36 rj1byte4_36 rj1byte3_36 rj1byte2_36 rj1byte1_36 rj1byte0_36 dd 11011101 rj1byte7_35 rj1byte6_35 rj1byte5_35 rj1byte4_35 rj1byte3_35 rj1byte2_35 rj1byte1_35 rj1byte0_35 de 11011110 rj1byte7_34 rj1byte6_34 rj1byte5_34 rj1byte4_34 rj1byte3_34 rj1byte2_34 rj1byte1_34 rj1byte0_34 df 11011111 rj1byte7_33 rj1byte6_33 rj1byte5_33 rj1byte4_33 rj1byte3_33 rj1byte2_33 rj1byte1_33 rj1byte0_33 e0 11100000 rj1byte7_32 rj1byte6_32 rj1byte5_32 rj1byte4_32 rj1byte3_32 rj1byte2_32 rj1byte1_32 rj1byte0_32 e1 11100001 rj1byte7_31 rj1byte6_31 rj1byte5_31 rj1byte4_31 rj1byte3_31 rj1byte2_31 rj1byte1_31 rj1byte0_31 e2 11100010 rj1byte7_30 rj1byte6_30 rj1byte5_30 rj1byte4_30 rj1byte3_30 rj1byte2_30 rj1byte1_30 rj1byte0_30 e3 11100011 rj1byte7_29 rj1byte6_29 rj1byte5_29 rj1byte4_29 rj1byte3_29 rj1byte2_29 rj1byte1_29 rj1byte0_29 e4 11100100 rj1byte7_28 rj1byte6_28 rj1byte5_28 rj1byte4_28 rj1byte3_28 rj1byte2_28 rj1byte1_28 rj1byte0_28 e5 11100101 rj1byte7_27 rj1byte6_27 rj1byte5_27 rj1byte4_27 rj1byte3_27 rj1byte2_27 rj1byte1_27 rj1byte0_27 e6 11100110 rj1byte7_26 rj1byte6_26 rj1byte5_26 rj1byte4_26 rj1byte3_26 rj1byte2_26 rj1byte1_26 rj1byte0_64 e7 11100111 rj1byte7_25 rj1byte6_25 rj1byte5_25 rj1byte4_25 rj1byte3_25 rj1byte2_25 rj1byte1_25 rj1byte0_25
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 34 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: receive j1 path trace bytes ( continued ) e8 11101000 rj1byte7_24 rj1byte6_24 rj1byte5_24 rj1byte4_24 rj1byte3_24 rj1byte2_24 rj1byte1_24 rj1byte0_24 e9 11101001 rj1byte7_23 rj1byte6_23 rj1byte5_23 rj1byte4_23 rj1byte3_23 rj1byte2_23 rj1byte1_23 rj1byte0_23 ea 11101010 rj1byte7_22 rj1byte6_22 rj1byte5_22 rj1byte4_22 rj1byte3_22 rj1byte2_22 rj1byte1_22 rj1byte0_22 eb 11101011 rj1byte7_21 rj1byte6_21 rj1byte5_21 rj1byte4_21 rj1byte3_21 rj1byte2_21 rj1byte1_21 rj1byte0_21 ec 11101100 rj1byte7_20 rj1byte6_20 rj1byte5_20 rj1byte4_20 rj1byte3_20 rj1byte2_20 rj1byte1_20 rj1byte0_20 ed 11101101 rj1byte7_19 rj1byte6_19 rj1byte5_19 rj1byte4_19 rj1byte3_19 rj1byte2_19 rj1byte1_19 rj1byte0_19 ee 11101110 rj1byte7_18 rj1byte6_18 rj1byte5_18 rj1byte4_18 rj1byte3_18 rj1byte2_18 rj1byte1_18 rj1byte0_18 ef 11101111 rj1byte7_17 rj1byte6_17 rj1byte5_17 rj1byte4_17 rj1byte3_17 rj1byte2_17 rj1byte1_17 rj1byte0_17 f0 11110000 rj1byte7_16 rj1byte6_16 rj1byte5_16 rj1byte4_16 rj1byte3_16 rj1byte2_16 rj1byte1_16 rj1byte0_16 f1 11110001 rj1byte7_15 rj1byte6_15 rj1byte5_15 rj1byte4_15 rj1byte3_15 rj1byte2_15 rj1byte1_15 rj1byte0_15 f2 11110010 rj1byte7_14 rj1byte6_14 rj1byte5_14 rj1byte4_14 rj1byte3_14 rj1byte2_14 rj1byte1_14 rj1byte0_14 f3 11110011 rj1byte7_13 rj1byte6_13 rj1byte5_13 rj1byte4_13 rj1byte3_13 rj1byte2_13 rj1byte1_13 rj1byte0_13 f4 11110100 rj1byte7_12 rj1byte6_12 rj1byte5_12 rj1byte4_12 rj1byte3_12 rj1byte2_12 rj1byte1_12 rj1byte0_12 f5 11110101 rj1byte7_11 rj1byte6_11 rj1byte5_11 rj1byte4_11 rj1byte3_11 rj1byte2_11 rj1byte1_11 rj1byte0_11 f6 11110110 rj1byte7_10 rj1byte6_10 rj1byte5_10 rj1byte4_10 rj1byte3_10 rj1byte2_10 rj1byte1_10 rj1byte0_10 f7 11110111 rj1byte7_9 rj1byte6_9 rj1byte5_9 rj1byte4_9 rj1byte3_9 rj1byte2_9 rj1byte1_9 rj1byte0_9 f8 11111000 rj1byte7_8 rj1byte6_8 rj1byte5_8 rj1byte4_8 rj1byte3_8 rj1byte2_8 rj1byte1_8 rj1byte0_8 f9 11111001 rj1byte7_7 rj1byte6_7 rj1byte5_7 rj1byte4_7 rj1byte3_7 rj1byte2_7 rj1byte1_7 rj1byte0_7 fa 11111010 rj1byte7_6 rj1byte6_6 rj1byte5_6 rj1byte4_6 rj1byte3_6 rj1byte2_6 rj1byte1_6 rj1byte0_6 fb 11111011 rj1byte7_5 rj1byte6_5 rj1byte5_5 rj1byte4_5 rj1byte3_5 rj1byte2_5 rj1byte1_5 rj1byte0_5 fc 11111100 rj1byte7_4 rj1byte6_4 rj1byte5_4 rj1byte4_4 rj1byte3_4 rj1byte2_4 rj1byte1_4 rj1byte0_4 fd 11111101 rj1byte7_3 rj1byte6_3 rj1byte5_3 rj1byte4_3 rj1byte3_3 rj1byte2_3 rj1byte1_3 rj1byte0_3 fe 11111110 rj1byte7_2 rj1byte6_2 rj1byte5_2 rj1byte4_2 rj1byte3_2 rj1byte2_2 rj1byte1_2 rj1byte0_2 ff 11111111 rj1byte7_1 rj1byte6_1 rj1byte5_1 rj1byte4_1 rj1byte3_1 rj1byte2_1 rj1byte1_1 rj1byte0_1
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 35 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: transmit j1 path trace bytes re g ister 0xbf settin g s: tj1byte_rd = 1, bip_cnts = 0, rei_cnts = 0, rj1byte = 0 c0 11000000 tj1byte7_64 tj1byte6_64 tj1byte5_64 tj1byte4_64 tj1byte3_64 tj1byte2_64 tj1byte1_64 tj1byte0_64 c1 11000001 tj1byte7_63 tj1byte6_63 tj1byte5_63 tj1byte4_63 tj1byte3_63 tj1byte2_63 tj1byte1_63 tj1byte0_63 c2 11000010 tj1byte7_62 tj1byte6_62 tj1byte5_62 tj1byte4_62 tj1byte3_62 tj1byte2_62 tj1byte1_62 tj1byte0_62 c3 11000011 tj1byte7_61 tj1byte6_61 tj1byte5_61 tj1byte4_61 tj1byte3_61 tj1byte2_61 tj1byte1_61 tj1byte0_61 c4 11000100 tj1byte7_60 tj1byte6_60 tj1byte5_60 tj1byte4_60 tj1byte3_60 tj1byte2_60 tj1byte1_60 tj1byte0_60 c5 11000101 tj1byte7_59 tj1byte6_59 tj1byte5_59 tj1byte4_59 tj1byte3_59 tj1byte2_59 tj1byte1_59 tj1byte0_59 c6 11000110 tj1byte7_58 tj1byte6_58 tj1byte5_58 tj1byte4_58 tj1byte3_58 tj1byte2_58 tj1byte1_58 tj1byte0_58 c7 11000111 tj1byte7_57 tj1byte6_57 tj1byte5_57 tj1byte4_57 tj1byte3_57 tj1byte2_57 tj1byte1_57 tj1byte0_57 c8 11001000 tj1byte7_56 tj1byte6_56 tj1byte5_56 tj1byte4_56 tj1byte3_56 tj1byte2_56 tj1byte1_56 tj1byte0_56 c9 11001001 tj1byte7_55 tj1byte6_55 tj1byte5_55 tj1byte4_55 tj1byte3_55 tj1byte2_55 tj1byte1_55 tj1byte0_55 ca 11001010 tj1byte7_54 tj1byte6_54 tj1byte5_54 tj1byte4_54 tj1byte3_54 tj1byte2_54 tj1byte1_54 tj1byte0_54 cb 11001011 tj1byte7_53 tj1byte6_53 tj1byte5_53 tj1byte4_53 tj1byte3_53 tj1byte2_53 tj1byte1_53 tj1byte0_53 cc 11001100 tj1byte7_52 tj1byte6_52 tj1byte5_52 tj1byte4_52 tj1byte3_52 tj1byte2_52 tj1byte1_52 tj1byte0_52 cd 11001101 tj1byte7_51 tj1byte6_51 tj1byte5_51 tj1byte4_51 tj1byte3_51 tj1byte2_51 tj1byte1_51 tj1byte0_51 ce 11001110 tj1byte7_50 tj1byte6_50 tj1byte5_50 tj1byte4_50 tj1byte3_50 tj1byte2_50 tj1byte1_50 tj1byte0_50 cf 11001111 tj1byte7_49 tj1byte6_49 tj1byte5_49 tj1byte4_49 tj1byte3_49 tj1byte2_49 tj1byte1_49 tj1byte0_49 d0 11010000 tj1byte7_48 tj1byte6_48 tj1byte5_48 tj1byte4_48 tj1byte3_48 tj1byte2_48 tj1byte1_48 tj1byte0_48 d1 11010001 tj1byte7_47 tj1byte6_47 tj1byte5_47 tj1byte4_47 tj1byte3_47 tj1byte2_47 tj1byte1_47 tj1byte0_47 d2 11010010 tj1byte7_46 tj1byte6_46 tj1byte5_46 tj1byte4_46 tj1byte3_46 tj1byte2_46 tj1byte1_46 tj1byte0_46 d3 11010011 tj1byte7_45 tj1byte6_45 tj1byte5_45 tj1byte4_45 tj1byte3_45 tj1byte2_45 tj1byte1_45 tj1byte0_45 d4 11010100 tj1byte7_44 tj1byte6_44 tj1byte5_44 tj1byte4_44 tj1byte3_44 tj1byte2_44 tj1byte1_44 tj1byte0_44 d5 11010101 tj1byte7_43 tj1byte6_43 tj1byte5_43 tj1byte4_43 tj1byte3_43 tj1byte2_43 tj1byte1_43 tj1byte0_43 d6 11010110 tj1byte7_42 tj1byte6_42 tj1byte5_42 tj1byte4_42 tj1byte3_42 tj1byte2_42 tj1byte1_42 tj1byte0_42 d7 11010111 tj1byte7_41 tj1byte6_41 tj1byte5_41 tj1byte4_41 tj1byte3_41 tj1byte2_41 tj1byte1_41 tj1byte0_41 d8 11011000 tj1byte7_40 tj1byte6_40 tj1byte5_40 tj1byte4_40 tj1byte3_40 tj1byte2_40 tj1byte1_40 tj1byte0_40 d9 11011001 tj1byte7_39 tj1byte6_39 tj1byte5_39 tj1byte4_39 tj1byte3_39 tj1byte2_39 tj1byte1_39 tj1byte0_39 da 11011010 tj1byte7_38 tj1byte6_38 tj1byte5_38 tj1byte4_38 tj1byte3_38 tj1byte2_38 tj1byte1_38 tj1byte0_38 db 11011011 tj1byte7_37 tj1byte6_37 tj1byte5_37 tj1byte4_37 tj1byte3_37 tj1byte2_37 tj1byte1_37 tj1byte0_37 dc 11011100 tj1byte7_36 tj1byte6_36 tj1byte5_36 tj1byte4_36 tj1byte3_36 tj1byte2_36 tj1byte1_36 tj1byte0_36 dd 11011101 tj1byte7_35 tj1byte6_35 tj1byte5_35 tj1byte4_35 tj1byte3_35 tj1byte2_35 tj1byte1_35 tj1byte0_35 de 11011110 tj1byte7_34 tj1byte6_34 tj1byte5_34 tj1byte4_34 tj1byte3_34 tj1byte2_34 tj1byte1_34 tj1byte0_34 df 11011111 tj1byte7_33 tj1byte6_33 tj1byte5_33 tj1byte4_33 tj1byte3_33 tj1byte2_33 tj1byte1_33 tj1byte0_33 e0 11100000 tj1byte7_32 tj1byte6_32 tj1byte5_32 tj1byte4_32 tj1byte3_32 tj1byte2_32 tj1byte1_32 tj1byte0_32 e1 11100001 tj1byte7_31 tj1byte6_31 tj1byte5_31 tj1byte4_31 tj1byte3_31 tj1byte2_31 tj1byte1_31 tj1byte0_31 e2 11100010 tj1byte7_30 tj1byte6_30 tj1byte5_30 tj1byte4_30 tj1byte3_30 tj1byte2_30 tj1byte1_30 tj1byte0_30 e3 11100011 tj1byte7_29 tj1byte6_29 tj1byte5_29 tj1byte4_29 tj1byte3_29 tj1byte2_29 tj1byte1_29 tj1byte0_29 e4 11100100 tj1byte7_28 tj1byte6_28 tj1byte5_28 tj1byte4_28 tj1byte3_28 tj1byte2_28 tj1byte1_28 tj1byte0_28 e5 11100101 tj1byte7_27 tj1byte6_27 tj1byte5_27 tj1byte4_27 tj1byte3_27 tj1byte2_27 tj1byte1_27 tj1byte0_27 e6 11100110 tj1byte7_26 tj1byte6_26 tj1byte5_26 tj1byte4_26 tj1byte3_26 tj1byte2_26 tj1byte1_26 tj1byte0_26
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 36 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture ma p ( continued ) table 14. device re g ister ma p ( continued ) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block registers 0xc00xff: transmit j1 path trace bytes ( continued ) e7 11100111 tj1byte7_25 tj1byte6_25 tj1byte5_25 tj1byte4_25 tj1byte3_25 tj1byte2_25 tj1byte1_25 tj1byte0_25 e8 11101000 tj1byte7_24 tj1byte6_24 tj1byte5_24 tj1byte4_24 tj1byte3_24 tj1byte2_24 tj1byte1_24 tj1byte0_24 e9 11101001 tj1byte7_23 tj1byte6_23 tj1byte5_23 tj1byte4_23 tj1byte3_23 tj1byte2_23 tj1byte1_23 tj1byte0_23 ea 11101010 tj1byte7_22 tj1byte6_22 tj1byte5_22 tj1byte4_22 tj1byte3_22 tj1byte2_22 tj1byte1_22 tj1byte0_22 eb 11101011 tj1byte7_21 tj1byte6_21 tj1byte5_21 tj1byte4_21 tj1byte3_21 tj1byte2_21 tj1byte1_21 tj1byte0_21 ec 11101100 tj1byte7_20 tj1byte6_20 tj1byte5_20 tj1byte4_20 tj1byte3_20 tj1byte2_20 tj1byte1_20 tj1byte0_20 ed 11101101 tj1byte7_19 tj1byte6_19 tj1byte5_19 tj1byte4_19 tj1byte3_19 tj1byte2_19 tj1byte1_19 tj1byte0_19 ee 11101110 tj1byte7_18 tj1byte6_18 tj1byte5_18 tj1byte4_18 tj1byte3_18 tj1byte2_18 tj1byte1_18 tj1byte0_18 ef 11101111 tj1byte7_17 tj1byte6_17 tj1byte5_17 tj1byte4_17 tj1byte3_17 tj1byte2_17 tj1byte1_17 tj1byte0_17 f0 11110000 tj1byte7_16 tj1byte6_16 tj1byte5_16 tj1byte4_16 tj1byte3_16 tj1byte2_16 tj1byte1_16 tj1byte0_16 f1 11110001 tj1byte7_15 tj1byte6_15 tj1byte5_15 tj1byte4_15 tj1byte3_15 tj1byte2_15 tj1byte1_15 tj1byte0_15 f2 11110010 tj1byte7_14 tj1byte6_14 tj1byte5_14 tj1byte4_14 tj1byte3_14 tj1byte2_14 tj1byte1_14 tj1byte0_14 f3 11110011 tj1byte7_13 tj1byte6_13 tj1byte5_13 tj1byte4_13 tj1byte3_13 tj1byte2_13 tj1byte1_13 tj1byte0_13 f4 11110100 tj1byte7_12 tj1byte6_12 tj1byte5_12 tj1byte4_12 tj1byte3_12 tj1byte2_12 tj1byte1_12 tj1byte0_12 f5 11110101 tj1byte7_11 tj1byte6_11 tj1byte5_11 tj1byte4_11 tj1byte3_11 tj1byte2_11 tj1byte1_11 tj1byte0_11 f6 11110110 tj1byte7_10 tj1byte6_10 tj1byte5_10 tj1byte4_10 tj1byte3_10 tj1byte2_10 tj1byte1_10 tj1byte0_10 f7 11110111 tj1byte7_9 tj1byte6_9 tj1byte5_9 tj1byte4_9 tj1byte3_9 tj1byte2_9 tj1byte1_9 tj1byte0_9 f8 11111000 tj1byte7_8 tj1byte6_8 tj1byte5_8 tj1byte4_8 tj1byte3_8 tj1byte2_8 tj1byte1_8 tj1byte0_8 f9 11111001 tj1byte7_7 tj1byte6_7 tj1byte5_7 tj1byte4_7 tj1byte3_7 tj1byte2_7 tj1byte1_7 tj1byte0_7 fa 11111010 tj1byte7_6 tj1byte6_6 tj1byte5_6 tj1byte4_6 tj1byte3_6 tj1byte2_6 tj1byte1_6 tj1byte0_6 fb 11111011 tj1byte7_5 tj1byte6_5 tj1byte5_5 tj1byte4_5 tj1byte3_5 tj1byte2_5 tj1byte1_5 tj1byte0_5 fc 11111100 tj1byte7_4 tj1byte6_4 tj1byte5_4 tj1byte4_4 tj1byte3_4 tj1byte2_4 tj1byte1_4 tj1byte0_4 fd 11111101 tj1byte7_3 tj1byte6_3 tj1byte5_3 tj1byte4_3 tj1byte3_3 tj1byte2_3 tj1byte1_3 tj1byte0_3 fe 11111110 tj1byte7_2 tj1byte6_2 tj1byte5_2 tj1byte4_2 tj1byte3_2 tj1byte2_2 tj1byte1_2 tj1byte0_2 ff 11111111 tj1byte7_1 tj1byte6_1 tj1byte5_1 tj1byte4_1 tj1byte3_1 tj1byte2_1 tj1byte1_1 tj1byte0_1
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 37 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion hexadecimal notation is used in both the address and the reset default columns in all the re g ister description tables in this section. device-level control, alarm, and mask bits ( 0x000x16 ) table 15. re g isters 0x000x16: device-level control, alarm, and mask bits address ( hex ) bit # name function reset default ( hex ) 0x00 the bits in the re g ister 0x00 are used for device-level con- trol and error reportin g . 0x00 7 test_cnt factor y test mode. test_cnt = 1 forces all internal counters to test mode and is intended for factor y use onl y . this bit should alwa y s be set to 0. 6 b1errins b1errins, b2errins, and b3errins. b1errins, b2errins, and b3errins all cause continuous bip-8 errors to be transmitted in their respective bip-8 values. 5 b2errins 4 b3errins 3 latch_cnt latch count. the device has a number of bip, rei, and pointer ad j ustment counters that are all updated when the latch_cnt bit is written from 0 to 1. nothin g happens when the bit is written from 1 to 0. the onl y internal counter that is not updated b y this bit is the test pattern counter. 2 blueclksel the device can accept a blue si g nal clock at either the exact ds1 rate ( blueclksel = 0 ) , or at 16 times the ds1 rate ( blueclksel = 1 ) . 1 bipblkcnt bip error counter or bip block counter. the bipblkcnt bit is used to determine whether the bip counters count the number of bip errors ( bipblkcnt = 0 ) or the number of bip blocks that contain errors ( bipblkcnt = 1 ) . 0reserved.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 38 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x01 the bits in re g ister 0x01 are used to provision device-level control bits. the functions of these bits are described below. 0x00 7 rei_en rei_enable. when rei_en = 1, the device will automati- call y insert the appropriate rei into the transmitted z2, g1, v5 overhead b y tes whenever it receives bip errors. if rei_en = 0, then the automatic insertion of rei is dis- abled. 6 auto_lrdi when auto_lrdi = 1, the device will automaticall y insert line rdi. 5 txpaisins when txpaisins = 1, the device will write all 1s into the pointer b y tes ( h1h3 ) and all of the s y nchronous pa y load envelope ( spe ) . 4 djactl the djactl is used to enable the use of the built-in di g ital j itter attenuators. when djactl = 0, the g apped ds1/e1 clock and data are transmitted b y the device; otherwise, the smoothed clock and data are transmitted. 3reserved. 2 sts1scr sts-1_scramble. when sts1scr = 1, the device scram- bles the out g oin g sts-1 frame accordin g to the sonet frame s y nchronous scramblin g se q uence 1 + x 6 + x 7 . the se q uence is reset to 1111111 at the be g innin g of the b y te followin g the c1 b y te and scrambles all of the sts-1 data except the a1, a2, and c1 b y tes. when this bit is 0, then the transmit data is not scrambled. 1 sts1dscr sts-1_descramble. when sts1dscr = 1, the device descrambles the incomin g sts-1 frame accordin g to the sonet frame s y nchronous descramblin g se q uence 1 + x 6 + x 7 . the se q uence is reset to 1111111 at the be g in- nin g of the b y te followin g the c1 b y te and descrambles all of the sts-1 data except the a1, a2, and c1 b y tes. when this bit is 0, then the received data is not descrambled. 0 sts1lb sts-1_loopback. when sts1lb = 1, the transmitted data is looped back to the receive side. when this bit is 0, the device uses the received data.
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 39 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x02 the bits in re g ister 0x02 are used to set the ed g es that retime data into and out of the device. 0x00 7 rxserial receive serial data, transmit serial data. both the rxserial and txserial bits are used to set the t y pe of sts-1 data. when either serial bit is written to 1, the sts-1 rail runs in serial mode; otherwise, the sts-1 rail runs in parallel mode. 6 txserial 5 rxparity both the rxparity and txparity bits determine the t y pe of parit y for data buses. when these bits are written with 1, odd parit y is used; otherwise, even parit y is used. 4 txparity 3 rxsts1edge when the ed g e re g ister bits are set to 1, the data is retimed ( either in or out ) b y the risin g clock ed g e; when set to a lo g ic 0, the data is retimed b y the fallin g clock ed g e. note that the tsts1serial data alwa y s comes out on the ris- in g ed g e of the tsts1clkout. note: the txsts1edge ( bit 2 ) should alwa y s be set to 0 to avoid potential race condition inside the device. 2txsts1edge 1 rxds1edge 0 txds1edge
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 40 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x03 the bits in re g ister 0x03 are used to report problems at the receive sts-1 level. 0x00 7 traceer the device monitors the received j1 b y te for path trace mismatches. when the received j1 b y te pattern does not match the previousl y received pattern, then traceer = 1. this is an event bit and is held until read. 6 rxparer rxparer = 1 reports a parit y violation on the receive sts-1 data bus when in parallel mode. this is an event bit and is held until read. 5reserved. 4 h4lomf the device monitors the incomin g h4 b y te for loss of multi- frame indication ( h4lomf = 1 ) . this is an event bit and is held until read. 3 sts1pais sts1pais = 1 reports path ais as detected b y the receive pointer interpreter. this is a current state bit with a mini- mum persistence of 375 m s. the indications reset if the condition is no lon g er true. 2 sts1lop sts1lop = 1 reports a loss of sts-1 pointer. this is a cur- rent state bit with a minimum persistence of 125 m s. the indications reset if the condition is no lon g er true. 1 sts1lof sts1lof = 1 reports an out of frame condition that per- sists for more than 3 ms. this is a current state bit with a minimum persistence of 3 ms. the indications reset if the condition is no lon g er true. 0 sts1oof sts1oof = 1 reports an out of frame condition on the receive sts-1 si g nal. this is a current state bit with a mini- mum persistence of 500 m s. the indications reset if the condition is no lon g er true. 0x04 7 traceermsk the bits in re g ister 0x04 are used to mask the contributions of the bits in re g ister 0x03 to the microprocessor interrupt output, int. when an y of these bits are at a lo g ic 1 level, the correspondin g bit in re g ister 0x03 is masked from con- tributin g to the output interrupt. the reset default for this re g ister masks all of the bits in re g ister 0x03. bit 5 is reserved. 0xff 6 rxparermsk 5 4h4lomfmsk 3 sts1paismsk 2 sts1lopmsk 1 sts1lofmsk 0 sts1oofmsk
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 41 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x05 the bits in re g ister 0x05 are used to report problems at the receive ds1/e1 and vt level. the bits in this re g ister are composite bits. the bits that report the problems at the vt level are located in 28 separate re g isters ( one for each vt ) as described below. these composite bits are placed in the re g ister map to determine which t y pe of error was detected. when an y one of the 28 vt bits indicates an error, the correspondin g composite bit indicates an error. 0x00 7 esofcom esofcom = 1 reports that the device has experienced either a receive or a transmit elastic store overflow. this is an event bit and is held until read. 6 vtsizecom vtsizecom = 1 reports incorrect vt size bits. the valid vt size bits are 11 for vt1.5 and 10 for vt2. 5 vtlopcom vtlopcom = 1 reports lop-v. 4 vtrfirdicom vtrfirdicom = 1 reports the fact that the vt rfi/rdi bits have been received as a new consistent value for three consecutive superframes. this is an event bit and is held until read. 3 vtaiscom vtaiscom = 1 reports the fact that the v1 and v2 pointer b y tes are all 1s for three consecutive superframes. 2 vtlabcom vtlabcom = 1 reports chan g e of state of the vt label. in order for this bit to be set, the device must detect three consecutive consistent new values for the vt label. this is an event bit and is held until read. 1 aisloccom aisloccom = 1 reports an ais or loc condition on ds1/ e1. this is a current state bit with a minimum persistence of 2 ms. the indications reset if the condition is no lon g er true. 0 sts1los sts1los = 1 reports an sts-1 loss of si g nal. the bits in re g ister 0x91 are used to set the number of 6.48 mhz clock periods re q uired to declare received sts-1 loss of si g nal. if this value is 0x00, then sts1los is not declared. this is a current state bit with a minimum persistence of 250 m s. the indications reset if the condition is no lon g er true.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 42 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x06 7 esofmsk the bits in re g ister 0x06 are used to mask the contributions of the bits in re g ister 0x05 to the microprocessor interrupt output, int. when an y of these bits is 1, the correspondin g bit in re g ister 0x05 is masked from contributin g to the out- put interrupt. the reset default for this re g ister masks all of the bits in re g ister 0x05. 0xff 6 vtsizemsk 5vtlopmsk 4 vtrfirdimsk 3vtaismsk 2vtlabmsk 1aislocmsk 0 sts1losmsk 0x07 this re g ister reports the hardware selected device mode. 0x01 71 reserved. these bits are set to 0 at reset. 0 ds1_e1n this bit reports the ds1_e1n value from the device input pin. 0x08 the bits in re g ister 0x08 are used to confi g ure the test pat- tern g enerator and detector. 0x00 7 latch_tp a 0 to 1 transition on latch_tp causes the runnin g error count to be latched and presented to the microprocessor. 6 rcv_frame rcv_frame = 1 causes a framed test pattern to be expected; a 0 causes an unframed test pattern to be expected. 5 rcv_pat-1 rcv_pat [ 1:0 ] determines the receive test pattern se q uence where 00 = qrss, 01 = 2 23 C 1, 10 = 2 20 C 1, 11 = 2 15 C 1. 4 rcv_pat-0 3 error_ins error_ins causes a sin g le error to be inserted in the data ( not frame ) bits after a 0 to 1 transition. 2 xmt_frame xmt_frame = 1 causes a framed test pattern to be g en- erated; a 0 causes an unframed test pattern to be g ener- ated. 1 xmt_pat-1 xmtpat- [ 1:0 ] determines the transmit test pattern se q uence where 00 = qrss, 01 = 2 23 C 1, 10 = 2 20 C 1, 11 = 2 15 C 1. 0 xmt_pat-0
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 43 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x09 the bits in re g ister 0x09 are used to set up the test pattern. 0x00 7 tp_ds1e1n tp_ds1e1n = 1 sets the frame se q uence to ds1; tp_ds1e1n = 0 sets the frame se q uence to e1. 6 tp_invert tp_invert = 1 forces the test pattern se q uence to be inverted. 5 tpdropside when tpdropside = 1, the test pattern is dropped from the spe drop lo g ic. the ds1/e1 output that is dropped is described in the microprocessor interface description ( con- tinued ) section on pa g e 50. when tpdropside = 0, the ds1/e1 that is dropped is the same as described in the ds1/e1 insertion selection section on pa g e47. 4 tpdrop-4 the tpdrop [ 4:0 ] bits are used to select the vt that needs to be dropped. 3tpdrop-3 2tpdrop-2 1tpdrop-1 0tpdrop-0 0x0a the bits in re g ister 0x0a indicate the condition of the test pattern detector. 0x80 7 tpoos if the test pattern detector has been able to s y nchronize on the dropped si g nal, then tpoos = 0. 6 tperr-6 when tpoos = 0, then the tperr- [ 6:0 ] bits are used to keep count of the number of bit errors the test pattern detector has seen. this error count is cleared when the re g ister is read b y the microprocessor. 5tperr-5 4tperr-4 3tperr-3 2tperr-2 1tperr-1 0tperr-0 0x0b 70 f2- [ 7:0 ] the f2- [ 7:0 ] bits in re g ister 0x0b are used to report the f2 receive b y te in the path overhead. 0x00 0x0c 70 c2- [ 7:0 ] the c2- [ 7:0 ] bits in re g ister 0x0c are used to report the received c2 label b y te in the path overhead. the default value for this re g ister indicates path une q uipped. 0x00
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 44 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x0d the bits in re g ister 0x0d are used to report path and sec- tion overhead. 0x00 7g1-5the g1- [ 5:8 ] are used to report the four least si g nificant bits of the g1 path overhead b y te. 6g1-6 5g1-7 4g1-8 3reserved. 2 k2-6 the k2- [ 6:8 ] bits are used to report the three least si g nifi- cant bits of the k2 section overhead b y te. 1k2-7 0k2-8 0x0e the bits in re g ister 0x0e are used to set the number of con- secutive, consistent values re q uired b y re g isters 0x0b and 0x0c before updatin g their values. 0x33 7 c2#det-3 the c2#det- [ 3:0 ] bits are used to set the number of con- secutive and consistent values re q uired before updatin g c2- [ 7:0 ] bits in re g ister 0x0c. 6 c2#det-2 5 c2#det-1 4 c2#det-0 3 f2#det-3 the f2#det- [ 3:0 ] bits are used to set the number of con- secutive and consistent values re q uired before updatin g f2- [ 7:0 ] bits in re g ister 0x0b. valid values for this re g ister ran g e from 3 to 15. an y value less than 3 defaults to 2 inside the device. 2f2#det-2 1f2#det-1 0f2#det-0 0x0f the bits in re g ister 0x0f are used to set the number of con- secutive, consistent values re q uired b y re g ister 0x0d before updatin g their values. 0x33 7 g1#det-3 the g1#det- [ 3:0 ] bits are used to set the number of con- secutive and consistent values re q uired before updatin g g1- [ 5:8 ] bits in re g ister 0x0d. 6g1#det-2 5g1#det-1 4g1#det-0 3 k2#det-3 the k2#det- [ 3:0 ] bits are used to set the number of con- secutive and consistent values re q uired before updatin g k2- [ 6:8 ] bits in re g ister 0x0d. valid values for this re g ister ran g e from 3 to 15. an y value less than 3 defaults to 2 inside the device. 2k2#det-2 1k2#det-1 0k2#det-0 0x10 70 f2ins- [ 7:0 ] the f2ins- [ 7:0 ] bits in re g ister 0x10 are used to set the values to be transmitted in the f2 b y te. 0x00
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 45 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x11 the bits in re g ister 0x11 are used to set the values to be transmitted in the g1 and k2 b y tes. 0x00 7g1ins-5the g1ins- [ 5:8 ] bits are used to set values to be transmit- ted in the four least si g nificant bits of the g1 b y te. the g1 b y te is written b y the microprocessor. 6g1ins-6 5g1ins-7 4g1ins-8 3reserved. 2 k2ins-6 the k2ins- [ 6:8 ] bits are used to set the values to be trans- mitted in the three least si g nificant bits of the k2 b y te. auto_lrdi bit ( bit 6 of re g ister 0x01 ) should be set to 0 for k2ins- [ 6:8 ] insertion ( i.e., k2 insertion ) throu g h the microprocessor interface. 1k2ins-7 0k2ins-8 0x12 the bits in re g ister 0x12 are used to set the bus mode of operation for both the transmit and receive sides. 0x24 76 reserved. 5 rbusmode the rbusmode bit sets the sts-1 receive side of the device to the bus mode of operation when a 1; otherwise, the device is set to nonbus mode. 4 rbuspos-1 the rbuspos- [ 1:0 ] sets the time slot for the receive side. 00 causes the receive side not to listen. otherwise, the time slots are determined b y the binar y value of these bits as follows: 01 = time slot 1 10 = time slot 2 11 = time slot 3 3rbuspos-0 2 tbusmode the tbusmode bit sets the sts-1 transmit side of the device to the bus mode of operation when a 1; otherwise, the device is set to nonbus mode. 1 tbuspos-1 the tbuspos- [ 1:0 ] sets the time slot for the transmit sides. 00 causes the transmit side not to transmit. other- wise, the time slots are determined b y the binar y value of these bits as follows: 01 = time slot 1 10 = time slot 2 11 = time slot 3 0 tbuspos-0
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 46 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 15 . re g isters 0x000x16: device-level control, alarm, and mask bits ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x13 74 reserved. 0x00 3 s1ins-3 the s1ins- [ 3:0 ] bits in re g ister 0x13 are used to set the four least si g nificant bits of the s1 path overhead b y te. 2s1ins-2 1s1ins-1 0s1ins-0 0x14 the bits in re g ister 0x14 are for the s1 path overhead b y te. 0x30 7 s1#det-3 the s1#det- [ 3:0 ] bits are used to set the number of con- secutive, consistent values re q uired b y the receive s1 b y te before updatin g the value. valid values for these re g isters ran g e from 3 to 15. an y value less than 3 defaults to 2 inside the device. 6s1#det-2 5s1#det-1 4s1#det-0 3 s1-3 the s1- [ 3:0 ] bits are used to report the four least si g nificant bits of the s1 path overhead b y te. 2s1-2 1s1-1 0s1-0 0x15 70 devid- [ 7:0 ] devid- [ 7:0 ] bits in re g ister 0x15 are used to report the device id. 0x51 0x16 the devver- [ 3:0 ] bits in re g ister 0x16 are used to report the device version. an y time there are silicon chan g es that modif y the operation of this device, this re g ister will be incremented b y 1. notes: the reset default value is the device version. bits 74 are reserved. 74 3 devver-3 2 devver-2 1 devver-1 0 devver-0
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 47 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) ds1/e1 insertion selection table 16. re g isters 0x170x32: ds1/e1 insertion selection address ( hex ) bit # name function reset default ( hex ) 0x170x2b re g isters 0x170x2b report ds1 or e1 conditions. value is 0. 7 ds1/e1ais [ 1:21 ] the ds1/e1ais [ 1:21 ] bits report the received ds1/e1 ais condition. when an y of these bits is 1, the corre- spondin g ds1/e1 input has an ais condition. this value represents the current received state. the ais condition is not latched b y these bits. the indication is reset when the condition is no lon g er true. 6 ds1/e1loc [ 1:21 ] the ds1/e1loc [ 1:21 ] bits in bit 6 report the received ds1/e1 loss of clock condition. when an y of these bits is 1, the correspondin g ds1/e1 input has a received loss of clock condition. this value represents the cur- rent received state. the loss of clock condition is not latched b y these bits. the indication is reset when the condition is no lon g er true. 5 ds1/e1lb [ 1:21 ] the ds1/e1lb [ 1:21 ] bits in bit 5 are used to force ds1/ e1 loopback from output to input. when an y of these bits is 1, the correspondin g ds1/e1 input is overwritten b y the out g oin g ds1/e1 si g nal for that location. 4 ds1/e1ins4_ [ 1:21 ] the ds1/e1ins [ 4:0 ] _ [ 1:21 ] bits in re g isters 0x17 0x2b are used to select the ds1/e1 input for the trans- mit vt1.5 slots. the ds1/e1 selected corresponds to the decimal value of the pro g rammed 5 bits. if these bits contain 00000, the device will insert une q uipped into the correspondin g vt1.5 slot. if these bits contain 1110111110, the device will insert ais-v into the cor- respondin g vt1.5 slot. since the device defaults all 28 of these re g isters to the value 00000, all of the 28 vt1.5 slots be g in transmittin g une q uipped followin g reset. the value 11111 inserts the test pattern. addresses 0x17 0x32 correspond to vt1.5s as shown in table 17, pa g e 49. 3 ds1/e1ins3_ [ 1:21 ] 2 ds1/e1ins2_ [ 1:21 ] 1 ds1/e1ins1_ [ 1:21 ] 0 ds1/e1ins0_ [ 1:21 ]
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 48 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 16. re g isters 0x170x32: ds1/e1 insertion selection ( continued ) address ( hex ) bit # name function reset default ( hex ) 0x2c0x32 re g isters 0x170x32 report ds1 conditions. value is 0. 7 ds1ais [ 22:28 ] the ds1/e1ais [ 1:21 ] and ds1ais [ 22:28 ] bits report the received ds1 ais condition. when an y of these bits is 1, the correspondin g ds1 input has an ais condition. this value represents the current received state. the ais condi- tion is not latched b y these bits. the indication is reset when the condition is no lon g er true. 6 ds1loc [ 22:28 ] the ds1/e1loc [ 1:21 ] and ds1loc [ 22:28 ] bits in bit 6 report the received ds1 loss of clock condition. when an y of these bits is 1, the correspondin g ds1 input has a received loss of clock condition. this value represents the current received state. the loss of clock condition is not latched b y these bits. the indication is reset when the con- dition is no lon g er true. 5 ds1lb [ 22:28 ] the ds1/e1lb [ 1:21 ] and ds1lb [ 22:28 ] bits in bit 5 are used to force ds1 loopback from output to input. when an y of these bits is 1, the correspondin g ds1 input is overwrit- ten b y the out g oin g ds1 si g nal for that location. 4 ds1ins4_ [ 22:28 ] the ds1/e1ins [ 4:0 ] _ [ 1:21 ] and ds1ins [ 4:0 ] _ [ 22:28 ] bits in re g isters 0x170x32 are used to select the ds1 input for the transmit vt1.5 slots. the ds1 selected corresponds to the decimal value of the pro g rammed 5 bits. if these bits contain 00000, the device will insert une q uipped into the correspondin g vt1.5 slot. if these bits contain 11101 11110, the device will insert ais-v into the correspondin g vt1.5 slot. since the device defaults all 28 of these re g is- ters to the value 00000, all of the 28 vt1.5 slots be g in transmittin g une q uipped followin g reset. the value 11111 inserts the test pattern. addresses 0x170x32 correspond to vt1.5s as shown in table 17, pa g e 49. 3 ds1ins3_ [ 22:28 ] 2 ds1ins2_ [ 22:28 ] 1 ds1ins1_ [ 22:28 ] 0 ds1ins0_ [ 22:28 ]
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 49 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 17. ds1/e1 insertion selection format vt dro p selection ( 0x330x4e ) table 18. re g isters 0x330x4e: vt dro p selection 5 pro g rammed ds1/e1ins[4:0]_x bits vt1.5 # vt grou p # vt # address bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 17 0 0001 2 2 1 18 0 0010 3 3 1 19 0 0011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 26 5 4 30 1 1010 27 6 4 31 1 1011 28 7 4 32 1 1100 address ( hex ) bit # name function reset default ( hex ) 0x330x4e 7 reserved. value is 0. 6 rxesof [ 1:28 ] the rxesof [ 1:28 ] bits ( see vt drop selection re g isters, table 14, pa g e 25 ) report the receive elastic store overflow condition. when an y of these bits is 1, the correspondin g ds1/e1 output has experienced an elastic store overflow. this value is latched b y these bits until read b y the micro- processor. 5 txesof [ 1:28 ] the txesof [ 1:28 ] bits ( see control, alarm, and mask bit re g isters, table 14, pa g e 23 ) report the transmit elastic store overflow condition. when an y of these bits is 1, the correspondin g ds1/e1 input has experienced an elastic store overflow. this value is latched b y these bits until read b y the microprocessor. 4 vtdrop4_ [ 1:28 ] these bits in re g isters 0x330x4e are used to select the vt1.5 slot for the ds1/e1 outputs. the vt1.5 selected in table 17 corresponds to the decimal value of these pro- g rammed 5 bits. if these bits contain 00000, or 11101 11111, then the device inserts the followin g : 00000 = device does not transmit an y clock or data 11101 = device inserts a ds1 ais into the correspondin g ds1/e1 slot 11110 = device inserts a e1 ais into the correspondin g ds1/e1 slot 11111= device inserts the test pattern since the device defaults these bits in all 28 of these re g is- ters to 00000, there will be no clock or data in an y of the 28 ds1 or 21 e1 slots after reset. vtdrop [ 4:0 ] _ [ 1:28 ] , bits 0000111100, correspond to the specific vt1.5 streams as shown in table , pa g e 50. address 0x33 0x4e correspond to vts as shown in table 20, also on pa g e 50. 3 vtdrop3_ [ 1:28 ] 2 vtdrop2_ [ 1:28 ] 1 vtdrop1_ [ 1:28 ] 0 vtdrop0_ [ 1:28 ]
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 50 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 19. vt dro p selection format table 20. vt to address ma pp in g 5 pro g rammed ds1/e1ins[4:0]_x or vt dro p data bits vt1.5 dro p #vt grou p # vt # bit 4 bit 3 bit 2 bit 1 bit 0 1 1100001 2 2100010 3 3100011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 26 5411010 27 6411011 28 7411100 vt # address 133 234 335 ? ? ? ? 26 4c 27 4d 28 4e
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 51 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) tx vt overhead insertion control ( 0x4f0x6a ) table 21. re g isters 0x4f0x6a: tx vt overhead insertion control address ( hex ) bit # name function reset default ( hex ) 0x4f0x6a the bits in these re g isters provision the transmitted vt overhead b y te, v5. value is 0. 7 bip2erins [ 1:28 ] each bip2erins [ 1:28 ] bit = 1 forces the selected vt to transmit inverted bip-2 bits which causes the down- stream receiver to declare continuous bip-2 errors. 6 vtrfirdien [ 1:28 ] the vtrfirdien [ 1:28 ] bits control whether rdi-v bits are inserted automaticall y b y the device ( vtrfirdien [ 1:28 ] = 1 ) or manuall y b y the microprocessor ( vtrfirdien [ 1:28 ] = 0 ) . 5 vtrfiins [ 1:28 ] the vtrfiins [ 1:28 ] bits directl y pro g ram the transmitted rfi-v bits when the correspondin g vtrfirdien [ 1:28 ] bits = 1. 4 vtrdiins [ 1:28 ] the vtrdiins [ 1:28 ] bits directl y pro g ram the transmitted rdi-v bits when the correspondin g vtrfirdien [ 1:28 ] bits = 1. 3vtaisins [ 1:28 ] each vtaisins [ 1:28 ] bit = 1 forces ais-v to be written into the correspondin g vt slot. this consists of writin g all 1s into the selected vt slot. 2vtlabins2_ [ 1:28 ] the vtlabins [ 2:0 ] _ [ 1:28 ] bits directl y pro g ram the transmitted vt label bits. these bits are used to carr y une q uipped information ( vtlabins [ 2:0 ] _ [ 1:28 ] = 000 ) as well as specific pa y load mappin g s and ais-v. 1vtlabins1_ [ 1:28 ] 0vtlabins0_ [ 1:28 ]
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 52 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) rx vt dro p monitorin g ( 0x6b0x86 ) table 22. re g isters 0x6b0x86: rx vt dro p monitorin g address ( hex ) bit # name function reset default ( hex ) 0x6b0x86 the bits in re g ister 0x6b0x86 are used to report the vt slot status. value is 0. 7vtsizeer [ 1:28 ] the vtsizeer [ 1:28 ] bits report incorrect vt size bits when the value is 1. m = 1 reports an ais or loc condition on ds1/e1. these are current state bits with a minimum persistence of 500 m s. the indications reset if the condition is no lon g er true. 6vtlop [ 1:28 ] the vtlop [ 1:28 ] bits report vt loss of pointer when the value is 1. these are current state bits with a minimum per- sistence of 500 m s. the indications reset if the condition is no lon g er true. 5 vtrdi1_ [ 1:28 ] the vtrdi [ 1:0 ] _ [ 1:28 ] bits report vt rdi. these are cur- rent state bits with a minimum persistence of 500 m s. the indications reset if the condition is no lon g er true. 4 vtrdi0_ [ 1:28 ] 3vtais [ 1:28 ] each vtais [ 1:28 ] bit = 1 reports that the v1 and v2 pointer b y tes are all 1s for three consecutive superframes. these are current state bits with a minimum persistence of 1500 m s. the indications reset if the condition is no lon g er true. 2 vtlab2_ [ 1:28 ] the vtlab [ 2:0 ] _ [ 1:28 ] bits report the received vt labels. these bits have a minimum persistence of 500 m s. 1 vtlab1_ [ 1:28 ] 0 vtlab0_ [ 1:28 ] 0x87 70 reserved. 0x00
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 53 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 23. re g isters 0x880x89: si g nal override control address ( hex ) bit # name function reset default ( hex ) 0x88 the bits in re g ister 0x88 are used to override the ds1_e1n si g nal pin. these bits represent the seven vt groups and can be individuall y pro g rammed as follows. 0x00 7 tvtg-7 if tvtg-1 . . . 7 = 1, the si g nal will be ds1; otherwise, the si g nal will be e1. 6tvtg-6 5tvtg-5 4tvtg-4 3tvtg-3 2tvtg-2 1tvtg-1 0 toverride if toverride = 1, then the t y pe of si g nal in each vt group is determined b y the 7 tvtg bits. 0x89 the bits in re g ister 0x89 are used to override the ds1_e1n si g nal pin. these bits represent the seven vt groups and can be individuall y pro g rammed as follows. 0x00 7 rvtg-7 if rvtg-1 . . . 7 = 1, the si g nal will be ds1; otherwise, the si g nal will be e1. 6rvtg-6 5rvtg-5 4rvtg-4 3rvtg-3 2rvtg-2 1rvtg-1 0 roverride if roverride = 1, then the t y pe of si g nal in each vt group is determined b y the 7 rvtg bits.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 54 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) di g ital jitter attenuator controls ( 0x8a0x8f ) table 24. re g isters 0x8a0x8f: di g ital jitter attenuator controls address ( hex ) bit # name function reset default ( hex ) 0x8a0x8f the bits in re g isters 0x8a0x8f are used to control vari- ous aspects of the di g ital j itter attenuator. two pro g ramma- ble terms are used to set the 2nd order loop dampin g factor and natural fre q uenc y of the pll. these terms are the g ain threshold, set b y djagthr- [ 23:0 ] in re g isters 0x8d0x8f, and scale value, set b y djascale- [ 15:0 ] in re g isters 0x8b0x8c. the pll bandwidth can be set, usin g the above re g isters, to accommodate various s y stem constraints. see below. 0x8a 70 scalethr- [ 7:0 ] scale threshold. 0xff 0x8b 70 djascale- [ 15:8 ] scale value. 0x0f 0x8c 70 djascale- [ 7:0 ] 0xca 0x8d 70 djagthr- [ 23:16 ] gain threshold. 0x00 0x8e 70 djagthr- [ 15:8 ] 0xfe 0x8f 70 djagthr- [ 7:0 ] 0x50
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 55 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) table 25. re g ister 0x91: sts-1 los detect/test pattern ed g e control address ( hex ) bit # name function reset default ( hex ) 0x91 the bits in re g ister 0x91 are used to set the number of 6.48 mhz clock periods re q uired to declare received sts-1 loss of si g nal. the two least si g nificant bits have a dual pur- pose and can also be used to pro g ram the ed g e on which the qrss pattern g enerator and detector data is clocked. if this value is 0x00, then los is not declared; otherwise, the device looks for an all-zeros or all-ones input si g nal for the binar y e q uivalent of this value in clock periods to declare los. 0x00 7 losdet-7 these bits are used to set the number of 6.48 mhz clock periods re q uired to declare received sts-1 loss of si g nal. 6losdet-6 5losdet-5 4losdet-4 3losdet-3 2losdet-2 1losdet-1/ tp_edge-1 this bit has a dual purpose. it can either contribute to the above count or can be pro g rammed to set the ed g e on which the test pattern detector data is clocked in. when set to 0, the detector uses the risin g ed g e of the selected input clock to retime the data, or uses the fallin g ed g e otherwise. 0losdet-0/ tp_edge-0 this bit has a dual purpose. it can either contribute to the above count or can be pro g rammed to set the ed g e on which the test pattern g enerator data is clocked out. when set to 0, the g enerator uses the risin g ed g e of the blue si g - nal clock to retime the data, or uses the fallin g ed g e other- wise. 0x920xbe 70 reserved. value is 0.
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 56 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) block control ( 0xbf ) table 26. re g ister 0xbf: block control address ( hex ) bit # name function reset default ( hex ) 0xbf the bits in re g ister 0xbf control the information presented to the microprocessor from the re g isters 0xc00xff. these last 64 b y tes will displa y different results dependin g on the value pro g rammed into this b y te. a hierarch y of evaluation of these b y tes occurs in the followin g three wa y s presented in the description of bits 2, 1, 0. 0x00 74 reserved. these bits are set to 0. 3 tj1byte if tj1byte = 1, the transmitted j1 b y te values are pre- sented. these re g isters are read/write. an y values written into these re g isters will chan g e the j1 b y te values that are transmitted. 2 rj1byte if rj1byte = 1, the received j1 b y tes are presented ( read onl y) . 1 rei_cnts if rei_cnts = 1, rei error information is presented ( read onl y) . 0 bip_cnts if bip_cnts = 1, bip error information is presented, re g ardless of the values of the other bits in this re g ister ( read onl y) .
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 57 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) detected bip errors ( 0xc00xfd ) table 27. re g isters 0xc00xfd: detected bip errors note: bits in re g isters 0xc00xff can have one of four confi g urations, dependin g upon the settin g of re g ister 0xbf. when re g ister 0xbf is set for bip_cnts = 1, the b y tes in re g isters 0xc00xfd are used to count the number of bip errors detected b y the device. * these re g isters are not conti g uous, i.e., ever y other re g ister in this g roup is shown ( 0xc6, 0xc8, 0xca, . . . 0xfc ) per the re g ister map, pa g e 29 and pa g e 30. ? these re g isters are not conti g uous, i.e., ever y other re g ister in this g roup is shown ( 0xc7, 0xc9, 0xcb, . . . 0xfd ) per the re g ister map, pa g e 29 and pa g e 30. table 28. re g isters 0xfe, 0xff: received sonet/sdh pointer value when re g ister 0xbf is set for bip_cnts = 1, the b y tes in re g isters 0xfe0xff are used to report the received sonet/sdh pointer value. address ( hex ) bit # name function reset default ( hex ) 0xc0 70 b1bipcnt- [ 15:8 ] re g isters 0xc00xc5. the first six re g isters in the block, 0xc00xc5, are the bip errors detected b y b1, b2, and b3. value is 0. 0xc1 70 b1bipcnt- [ 7:0 ] 0xc2 70 b2bipcnt- [ 15:8 ] 0xc3 70 b2bipcnt- [ 7:0 ] 0xc4 70 b3bipcnt- [ 15:8 ] 0xc5 70 b3bipcnt- [ 7:0 ] 0xc6 0xfc* 7vt [ 1:28 ] ptr+3 re g isters 0xc60xfd. the remainin g re g isters in the block indicate the errors seen b y the bip-2 error detec- tors in the individual vt1.5 slots. since the bip-2 errors onl y re q uire 12 bits, the vt pointer increment counts are also presented in these re g isters. the values in all of these counters are latched b y the latch_cnt bit in re g ister 0x00. ( see the sts-1/au-3 terminate section, pa g e 16 and pa g e 17. ) value is 0. 6vt [ 1:28 ] ptr+2 5vt [ 1:28 ] ptr+1 4vt [ 1:28 ] ptr+0 3 bip2cnt11_ [ 1:28 ] 2 bip2cnt10_ [ 1:28 ] 1 bip2cnt9_ [ 1:28 ] 0 bip2cnt8_ [ 1:28 ] 0xc7 0xfd ? 7 bip2cnt7_ [ 1:28 ] 6 bip2cnt6_ [ 1:28 ] 5 bip2cnt5_ [ 1:28 ] 4 bip2cnt4_ [ 1:28 ] 3 bip2cnt3_ [ 1:28 ] 2 bip2cnt2_ [ 1:28 ] 1 bip2cnt1_ [ 1:28 ] 0 bip2cnt0_ [ 1:28 ] address ( hex ) bit # name function reset default ( hex ) 0xfe 70 sptr+ [ 7:0 ] re g ister 0xfe. the sptr+ [ 7:0 ] bits report the sonet pointer increment value. 0x00 0xff 70 sptrC [ 7:0 ] re g ister 0xff. the sptrC [ 7:0 ] bits report the sonet pointer decrement value. 0x00
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 58 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) detected rei errors ( 0xc00xfd ) table 29. re g isters 0xc00xfd: detected rei errors note: bits in re g isters 0xc00xff can have one of four confi g urations, dependin g upon the settin g of re g ister 0xbf. when re g ister 0xbf is set for bip_cnts = 0 and rei_cnts = 1, the b y tes in re g isters 0xc00xfd are used to count the number of rei errors detected b y the device. * these re g isters are not conti g uous, i.e., ever y other re g ister in this g roup is shown ( 0xc6, 0xc8, 0xca, . . . 0xfc ) per the re g ister map, pa g e 31 and pa g e 32. ? these re g isters are not conti g uous, i.e., ever y other re g ister in this g roup is shown ( 0xc7, 0xc9, 0xcb, . . . 0xfd ) per the re g ister map, pa g e 31 and pa g e 32. table 30. re g isters 0xfe0xff: reserved when re g ister 0xbf is set for bip_cnts = 0 and rei_cnts = 1, the b y tes in re g isters 0xfe0xff are reserved. address ( hex ) bit # name function reset default ( hex ) 0xc0 70 reserved. these bits are set to 0. value is 0. 0xc1 70 0xc2 70 b2rei- [ 15:8 ] re g isters 0xc20xc5. the re g isters, 0xc20xc5, are the rei errors detected b y b2 and b3 ( see the sts-1/au-3 terminate section, pa g e 16 and pa g e 17 ) . 0xc3 70 b2rei- [ 7:0 ] 0xc4 70 b3rei- [ 15:8 ] 0xc5 70 b3rei- [ 7:0 ] 0xc6 0xfc* 7vt [ 1:28 ] ptrC3 re g isters 0xc60xfd. the remainin g re g isters in the block indicate the errors seen b y the rei error detectors in the individual vt1.5 slots. since the vt rei errors onl y re q uire 11 bits, the vt pointer decrement counts are also presented in these re g isters. the values in all of these counters is latched b y the latch_cnt bit ( bit 3 ) in re g ister 0x00. ( see the sts-1/au-3 terminate section, pa g e 16 and pa g e 17. ) note: in re g isters 0xc60xfc, bit 3 is reserved. 6vt [ 1:28 ] ptrC2 5vt [ 1:28 ] ptrC1 4vt [ 1:28 ] ptrC0 3 2vtrei10_ [ 1:28 ] 1vtrei9_ [ 1:28 ] 0vtrei8_ [ 1:28 ] 0xc7 0xfd ? 7vtrei7_ [ 1:28 ] 6vtrei6_ [ 1:28 ] 5vtrei5_ [ 1:28 ] 4vtrei4_ [ 1:28 ] 3vtrei3_ [ 1:28 ] 2vtrei2_ [ 1:28 ] 1vtrei1_ [ 1:28 ] 0vtrei0_ [ 1:28 ] address ( hex ) bit # name function reset default ( hex ) 0xfe 70 reserved. these bits are set to 0. 0x00 0xff 70 0x00
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 59 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) re g ister architecture descri p tion ( continued ) receive j1 path trace b y tes ( 0xc00xff ) table 31. re g isters 0xc00xff: receive j1 path trace b y tes note: bits in re g isters 0xc00xff can have one of four confi g urations, dependin g upon the settin g of re g ister 0xbf. when re g ister 0xbf is set for bip_cnts = 0 and rei_cnts = 0 and rj1byte = 1, the b y tes in re g - isters 0xc00xff are used to read the received 64 path trace b y tes. transmit j1 path trace b y tes ( 0xc00xff ) table 32. re g isters 0xc00xff: transmit j1 path trace b y tes note: bits in re g isters 0xc00xff can have one of four confi g urations, dependin g upon the settin g of re g ister 0xbf. when re g ister 0xbf is set for bip_cnts = 0 and rj1byte = 1 and tj1byte = 1, the b y tes in re g is- ters 0xc00xff are used to provision the transmit 64 path trace b y tes. address ( hex ) bit # name function reset default ( hex ) 0xc00xff 7 rj1byte7_ [ 64:1 ] the receive j1 path trace b y te rj1byte [ 7:0 ] _64 corre- sponds to the first b y te in the 64-b y te se q uence, while the j1 path trace b y te rj1byte [ 7:0 ] _1 corresponds to the last b y te in the 64-b y te se q uence. these specified receive j1 b y te values are continuousl y written, modulo 64, into the 0xc00xff re g isters. if an y received b y te does not match the previousl y received b y te for its loca- tion, then traceer bit ( bit 7 ) in re g ister 0x03 is set to 1. value is 0. 6rj1byte6_ [ 64:1 ] 5rj1byte5_ [ 64:1 ] 4rj1byte4_ [ 64:1 ] 3rj1byte3_ [ 64:1 ] 2rj1byte2_ [ 64:1 ] 1rj1byte1_ [ 64:1 ] 0rj1byte0_ [ 64:1 ] address ( hex ) bit # name function reset default ( hex ) 0xc00xff 7 tj1byte7_ [ 64:1 ] the transmit j1 path trace b y te tj1byte [ 7:0 ] _64 corre- sponds to the first b y te in the 64-b y te se q uence, while the j1 path trace b y te tj1byte [ 7:0 ] _1 corresponds to the last b y te in the 64-b y te se q uence. these re g isters can be written b y the microprocessor. value is 0. 6tj1byte6_ [ 64:1 ] 5tj1byte5_ [ 64:1 ] 4tj1byte4_ [ 64:1 ] 3tj1byte3_ [ 64:1 ] 2tj1byte2_ [ 64:1 ] 1tj1byte1_ [ 64:1 ] 0tj1byte0_ [ 64:1 ]
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 60 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) i/o timin g the i/o timin g specifications for the microprocessor interface are g iven in table 33. the microprocessor interface pins use cmos i/o levels ( see pa g es 2022 for pin listin g s ) . all outputs, except the address/data bus ad [ 7:0 ] , are rated for a capacitive load of 50 pf. the ad [ 7:0 ] outputs are rated for a 100 pf load. the minimum read and write c y cle time is 200 ns for all device confi g urations. the read and write timin g dia g rams for all four microprocessor interface modes are shown in fi g ures 310. table 33. micro p rocessor interface i/o timin g s p ecifications symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 modes 1 & 2 address valid to as asserted ( read, write ) 5 t2 as asserted to address invalid ( read, write ) 10 t3 as asserted to ds asserted 0 t4 r/w hi g h ( read ) to ds asserted 25 t5 ds asserted ( read, write ) to dtack asserted 20 t6 dtack asserted to data valid ( read ) 24 t7 ds asserted ( read ) to data valid 44 t8 ds ne g ated ( read, write ) to as ne g ated t9 ds ne g ated ( read ) to data invalid 15 t10 ds ne g ated ( read ) to dtack ne g ated 15 t11 as ( read, write ) asserted width 75 t12 ds ( read ) asserted width 35 t13 as asserted to r/w low ( write ) 7 t14 r/w low ( write ) to ds asserted 20 t15 data valid to ds asserted ( write ) 7.5 t16 ds ne g ated to dtack ne g ated ( write ) 20 t17 ds ne g ated to data invalid ( write ) 7.5 t18 ds ( write ) asserted width 35 t19 modes 3 & 4 address valid to ale asserted low ( read, write ) 15 t20 ale asserted low ( read, write ) to address invalid 10 t21 ale asserted low to rd asserted ( read ) 30 t22 rd asserted ( read ) to data valid 90 t23 rd asserted ( read ) to rdy asserted 75 t24 rd ne g ated to data invalid ( read ) 25 t25 rd ne g ated to rdy ne g ated ( read ) 25 t26 ale asserted low to wr asserted ( write ) 35 t27 cs asserted to rdy asserted low 16 t28 data valid to wr asserted ( write ) 25 t29 wr asserted ( write ) to rdy asserted 73 t30 wr ne g ated to rdy ne g ated ( write ) 22 t31 wr ne g ated to data invalid 25 t32 ale asserted ( read, write ) width 150 t33 rd asserted ( read ) width 100 t34 wr asserted ( write ) width 100
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 61 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) i/o timin g ( continued ) 5-3685(f).br.4 fi g ure 3. mode 1read c y cle timin g ( mpmode = 0, mpmux = 0 ) 5-3686(f).br.5 fi g ure 4. mode 1write c y cle timin g ( mpmode = 0, mpmux = 0 ) t6 t7 t5 ds as cs minimum read cycle valid address valid data a[7:0] r/w t2 t3 t10 t9 t8 t4 t12 ad[7:0] dtack t11 t1 t14 t5 t15 ds as cs minimum write cycle valid address valid data a[7:0] r/w t2 t1 t13 t16 t17 t8 t18 ad[7:0] dtack t11
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 62 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) i/o timin g ( continued ) 5-3687(f)r.12 fi g ure 5. mode 2read c y cle timin g ( mpmode = 0, mpmux = 1 ) 5-3688(f)r.12 fi g ure 6. mode 2write c y cle timin g ( mpmode = 0, mpmux = 1 ) t6 t7 t5 ds as cs minimum read cycle valid data r/w t3 t10 t9 t8 t4 t12 ad[7:0] dtack t11 valid address valid address valid data t2 t1 valid address valid address valid data valid data cs as r/w ds dtack ad[7:0] minimum write cycle t11 t14 t8 t18 t16 t1 t13 t5 t2 t15 t17
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 63 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) i/o timin g ( continued ) 5-3689(f).br.4 fi g ure 7. mode 3read c y cle timin g ( mpmode = 1, mpmux = 0 ) 5-3690(f).br.3 fi g ure 8. mode 3write c y cle timin g ( mpmode = 1, mpmux = 0 ) minimum read cycle t32 valid address ale cs a[7:0] rd ad[7:0] rdy valid data t23 t25 t24 t22 t19 t27 t21 t20 t33 cs ale a[7:0] wr ad[7:0] rdy minimum write cycle t19 t32 t20 valid address t28 t34 t26 t31 t29 t30 t27 valid data
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 64 lucent technologies inc. micro p rocessor interface descri p tion ( continued ) i/o timin g ( continued ) 5-3691(f)r.12 fi g ure 9. mode 4read c y cle timin g ( mpmode = 1, mpmux = 1 ) 5-3692(f)r.13 fi g ure 10. mode 4write c y cle timin g ( mpmode = 1, mpmux = 1 ) cs ale rd ad[7:0] rdy minimum read cycle t32 t33 t22 t23 t25 t20 t27 t19 t21 t24 valid data valid data valid address valid address cs ale wr ad[7:0] rdy valid data valid address valid address valid data minimum write cycle t32 t26 t34 t29 t27 t30 t31 t28 t20 t19
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 65 lucent technologies inc. absolute maximum ratin g s stresses in excess of the absolute maximum ratin g s can cause permanent or latent dama g e to the device. these are absolute stress ratin g s onl y . functional operation of the device is not implied at these or an y other conditions in excess of those g iven in the operational sections of this device specification. exposure to absolute maximum rat- in g s for extended periods can adversel y affect device reliabilit y . table 34. absolute maximum ratin g s handlin g precautions althou g h protection circuitr y has been desi g ned into this device, proper precautions should be taken to avoid expo- sure to electrostatic dischar g e ( esd ) durin g handlin g and mountin g . lucent emplo y s a human-bod y model ( hbm ) and char g ed-device model ( cdm ) for esd-susceptibilit y testin g and protection desi g n evaluation. esd volta g e thresholds are dependent on the circuit parameters used in the defined model. no industr y -wide standard has been adopted for the cdm. however, a standard hbm ( resistance = 1500 w , capacitance = 100 pf ) is widel y used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained b y usin g these circuit parameters. parameter s y mbol min max unit power suppl y ( dc volta g e ) v dd C0.5 4.6 v input volta g ev i C0.3 5.5 v output volta g ev o 3.63v stora g e temperature t st g C65 125 c ambient operatin g temperature ran g et a C40 85 c table 35. esd threshold volta g e model volta g e ( volts ) hbm 2000 cdm ( all pins except corner pins ) 500 cdm ( all corner pins ) 1000
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 66 lucent technologies inc. o p eratin g conditions electrical characteristics table 37. lo g ic interface characteristics * 100 pf allowed for ad[7:0] ( pins 48 to 50 and 55 to 59 ) . table 36. recommended o p eratin g conditions parameter s y mbol min t yp max unit power suppl y ( dc volta g e ) v dd 3.14 3.3 3.46 v ground v ss 0.0v input volta g e, hi g hv ih v dd C 1.0 5.25 v input volta g e, low v il v ss 1.0 v ambient temperature t a C40 85 c power dissipation, ds1 ( t a = 23 c, v dd = 3.3 v ) : full loopback broadcast standb y p d 380 380 360 mw mw mw power dissipation, e1 ( t a = 23 c, v dd = 3.3 v ) : full loopback broadcast standb y 450 450 430 mw mw mw an internal 100 k w pull-up is provided on the ict , reset , cs , tck, tdi, tms, trst , rsts1data [ 7:0 ] , rsts1par, e1blueclk, rclk [ 28:1 ] , and rdata [ 28:1 ] pins. this re q uires these input pins to sink no more than 20 a. all buffers use cmos levels. parameter s y mbol test conditions min max unit input volta g e: low hi g h v il v ih gnd v dd C 1.0 1.0 v dd v v input leaka g ei l 1.0 a output volta g e: low hi g h v ol v oh C5.0 ma 5.0 ma gnd v dd C 1.0 0.5 v dd v v input capacitance c i 3.0pf load capacitance* c l 25 pf
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 67 lucent technologies inc. timin g characteristics o p erational timin g the operational timing parameters can be grouped separately for clocks, inputs, and outputs. table 38 lists the transmit and receive input clock specifications for this device. ( for definitions of the si g nal names, see the pin descriptions in table 1, pa g es 79. ) table 38. in p ut clock s p ecifications signal name parameter min max unit input clock signals tsts1clkin frequency 51.839 51.841 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % frequency 19.439 19.441 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % frequency 6.479 6.481 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % rclk[1:28] (ds1 mode) rclk[1:21] (e1 mode) frequency 1.5437 1.5443 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % frequency 2.0484 2.0476 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % rsts1clk frequency 51.839 51.841 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % jtag signal tck frequency 0.5 12 mhz clock pulse high time 40 60 % peak-to-peak jitter 1 % rise/fall time 15 ns
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 68 lucent technologies inc. timin g characteristics ( continued ) o p erational timin g ( continued ) table 39 lists the setup time (t su ) and hold time (t h ) specifications for the receive input and jtag signals. the digi- tal system interface timing is shown in figure 11. * these clock edges are programmable through the microprocessor interface. notes: - represents a low-to-hi g h transition. represents a hi g h-to-low transition. 5-5342(f)r.5 fi g ure 11. interface data timin g table 39. input timing specifications input name reference clk * setup time (t su ) hold time (t h ) unit min max min max receive signals tsts1sync tsts1clkin 5 2 ns rdata[1:28] rclk[1:28] - 50 40 ns rsts1data[7:0] rsts1clk - 15 2 ns rsts1par rsts1clk - 15 2 ns rsts1serial rsts1clk - 52ns jtag signal tdi tck - 50 50 ns clock in data in t su t h clock out data out t pd
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 69 lucent technologies inc. timin g characteristics (continued) o p erational timin g (continued) the output clock specifications are shown in table 40. * the duty-cycle distortion added to the tsts1clkout signal is 2% worst case when measured from 1.5 v in to 1.5 v out with a 2 ns rise time input. table 41 lists the propa g ation dela y ( t pd ) specifications for the output si g nals. the di g ital s y stem interface timin g is shown in fi g ure 11, pa g e 68. * propagation delay skew, t plh t phl, is 200 ps. notes: - represents a low-to-high transition. represents a high-to-low transition. table 40. output clock specifications signal name frequency test conditions rise time fall time unit t r t f min max min max tclk[1:28] (ds1 mode) 1.544 mhz 5% c l = 50 pf 30 30 ns tclk[1:28] (e1 mode) 2.048 mhz 5% c l = 50 pf 30 30 ns tsts1clkout * 51.84 mhz 5% c l = 15 pf 3 3 ns 19.44 mhz 5% c l = 15 pf 3 3 ns 6.48 mhz 5% c l = 15 pf 3 3 ns table 41. output timing specifications output name reference clk test conditions propagation delay * unit t pd min max transmit signals tdata[28:1] tclk[1:28] - c l = 25 pf 40 190 ns tsts1data[7:0] tsts1clkin - c l = 15 pf 2 12 ns tsts1par tsts1clkin - c l = 15 pf 2 12 ns tsts1data7 tsts1clkin - c l = 15 pf 0 3.5 ns jtag signal tdo tck c l = 50 pf 1.5 17 ns
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 70 lucent technologies inc. timin g characteristics (continued) transmit s y nc timin g in all transmit modes, the first bit/b y te of the j0, j1, and v1 b y tes are coincident with the s y nc pulse. the second and third pulses in this composite si g nal are onl y needed to force v1 superframe ali g nment. if there are three s y nc pulses as shown below, then v1 will be forced. the serial mode transmit s y nc timin g is shown below in fi g ure 12. 5-6347(f)r.1 note: the - s y mbol followed b y a number represents the bit number in the b y te. fi g ure 12. serial mode transmit s y nc timin g the bus mode transmit s y nc timin g is shown below in fi g ure 13. 5-6347(f).a note: the # s y mbol followed b y a number represents the active device on the bus. fi g ure 13. bus mode transmit s y nc timin g tsts1clk tsts1sync tsts1data j0-7 j0-6 j0-5 j0-4 j0-3 j0-2 j0-1 j0-0 j1-7 j1-6 j1-5 j1-4 j1-3 j1-2 j1-1 j1-0 v1-7 v1-6 v1-5 v1-4 v1-3 v1-2 v1-1 v1-0 tsts1clk tsts1sync tsts1data j0#1 j0#2 j0#3 j1#1 j1#2 j1#3 v1#1 v1#2 v1#3
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 71 lucent technologies inc. timin g characteristics (continued) transmit s y nc timin g ( continued ) the nonbus parallel mode transmit s y nc timin g is shown below in fi g ure 14. 5-6347(f).b fi g ure 14. nonbus parallel mode transmit s y nc timin g receive s y nc timin g the onl y receive mode that re q uires a s y nc pulse is the bus mode. the s y nc pulse is re q uired to ali g n the device to time slot #1. the bus parallel mode receive s y nc timin g is shown below in fi g ure 15. 5-6347(f).cr.1 note: the # s y mbol followed b y a number represents the active device on the bus. fi g ure 15. bus parallel mode receive s y nc timin g tsts1clk tsts1sync tsts1data j0 j1 v1 rsts1clk rsts1serial rsts1data j0#1 j0#2 j0#3 j1#1 j1#2 j1#3 v1#1 v1#2 v1#3
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 72 lucent technologies inc. t yp ical uses path termination multi p lex usin g the device without internal loopbacks results in an sdh/sonet path terminatin g multiplex, as shown in fi g ure 16. 5-4876(f)r.9 note: n represents 28 or 21 for ds1 or e1, respectivel y . fi g ure 16. sdh/sonet path termination multi p lex a pp lication di g ital cross connect usin g the device with sts-1 internal loopbacks results in a di g ital cross connect, as shown in fi g ure 17. 5-4878(f)r.8 note: n represents 28 or 21 for ds1 or e1, respectivel y . fi g ure 17. di g ital cross connect a pp lication ds1/e1 #1 in elastic store spe insertion logic vt generate elastic store vt generate spe generate sts-1 out spe drop logic vt terminate vt terminate spe locate sts-1 in spe terminate liu ds1/e1 #1 out ds1/e1 #n in liu ds1/e1 #n out sts/stm demux logic sts/stm mux logic jitter attenuate jitter attenuate tmpr28051 t7693 quad liu tmux03155 liu elastic store spe insertion logic vt generate elastic store vt generate spe generate spe drop logic vt terminate vt terminate spe locate spe terminate ds1/e1 liu ds1/e1 ds1/e1 ds1/e1 liu liu #1 in #n in #1 out #n out t7693 quad liu t7693 quad liu tmpr28051
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 73 lucent technologies inc. t yp ical uses ( continued ) test pattern usecom p lete s y stem the internal test pattern g enerator can be used in con j unction with ds1 or e1 liu devices that have built-in loop- backs ( such as the lucent t7698fl3/t7693 ) to do a complete s y stem test, as shown in fi g ure 18. 5-4879(f)r.7 fi g ure 18. test pattern usa g e for com p lete s y stem test pattern useend to end the internal test pattern g enerator can be used to test connectivit y within a link b y settin g up a test pattern inser- tion at one end and a drop at the other, as shown in fi g ure 19. 5-4880(f)r.7 fi g ure 19. test pattern usa g e for end-to-end o p eration liu test pattern insert test pattern drop liu test pattern drop loopback mode test pattern source loopback mode optional test pattern drop ds1/e1 in ds1/e1 ais ds1/e1 ais ds1/e1 in tmpr28051 mapper tmpr28051 mapper tmpr28051 test pattern insert test pattern drop test pattern source test pattern drop tmpr28051 mapper mapper
data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 74 lucent technologies inc. outline dia g ram 208-pin sqfp dimensions are in millimeters. 5-2196(f)r.14 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200
data sheet august 1999 tmpr28051 sts-1/au-3 (stm-0) mapper 75 lucent technologies inc. orderin g information ds99-068sont re p laces ds98-100tic to incor p orate the followin g u p dates 1. pa g e 1, added bulleted items concernin g 3.3 v operation, and alarm and control standards. 2. pa g e5, description ( continued ) section, replaced the lucent t7690/t7693 quad line transceiver interfacin g device with the lucent t7698fl3/t7693 quad line transceiver. 3. pa g e5, fi g ure 1, block dia g ram, clarified block flow. 4. pa g e 6, chan g ed pin 184 and all correspondin g references to tck. 5. pa g e 7, clarified pin 102. 6. pa g e10, or g anized nomenclature assumptions section from the text at the be g innin g of the description sec- tion. 7. pa g e 10pa g e 19, clarified block descriptions. 8. pa g e 14, 2nd para g raph, corrected the explanation of the reduced h4 codin g se q uence format from alternate between to take on the followin g values. 9. pa g e 23pa g e 36, updated re g ister map. 10. pa g e37pa g e 59, updated re g ister description text and placed text in tables. 11. pa g e42, table, re g isters 0x000x16: device-level control, alarm, and mask bits, corrected the test pat- tern se q uence for re g ister xmt_pat-0, bits 01 and 11 combinations. 12. pa g e 49, table 18, re g isters 0x330x4e: vt drop selection, corrected vtxdrop, bits 4 throu g h 0, to vt_drop [ 4:0 ] _ [ 1:28 ] . 13. pa g e 54, table 24, re g isters 0x8a0x8f: di g ital jitter attenuator controls, added the re g ister default val- ues. 14. pa g e 65, table 34, absolute maximum ratin g s, updated table, includin g input and output volta g es. 15. pa g e 65, table 35, esd threshold volta g e, added parameters and values. 16. pa g e 66, table 36, recommended operatin g conditions, updated to list 3.3 v power dissipation for ds1 and e1. 17. pa g e 67, table 38, input clock specifications, added to the document. 18. pa g e 69, table 40, output clock specifications, added to the document. 19. pa g e 70, transmit s y nc timin g section, expanded and corrected. 20. pa g e71, fi g ure 15, bus parallel mode receive s y nc timin g , corrected pin name. 21. pa g e 75, updated device code. 22. tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 2 of the device , tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 3 of the device , tmpr28051 sts-1/au-3 (stm-0) mapper device advisory for version 4 of the device , tmpr28051 sts-1/au-3 (stm-0) data addendum, included all printed advisories and an addendum throu g h version 4, each published in april 1999, ( ay99-026sont, ay99-027sont, ay99-028sont, da99-009sont ) . an advisor y was not issued for version 1 of the device. device code packa g etem p erature comcode ( orderin g number ) TMPR28051-3-SL5 208-pin sqfp C40 c to +85 c 108421678
for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) data sheet tmpr28051 sts-1/au-3 (stm-0) mapper august 1999 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved august 1999 ds99-068sont (replaces ds98-100tic)

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